[llvm] [AMDGPU] SIPeepholeSDWA: Add REG_SEQUENCE support (PR #133087)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900  -stop-after=si-peephole-sdwa -o - %s | FileCheck %s
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arsenm wrote:

I don't understand what this run line is doing, and it should probably be an llc error. Where is this starting? I'm suspecting it's forming the default empty function, codegenning that, and then it somehow merges with whatever MIR happened to be there from the initial parse?

https://github.com/llvm/llvm-project/pull/133087