[llvm] [WIP][AMDGPU][MC] Allow 128-bit rsrc register in MIMG instructions (PR #132264)

Fri Mar 28 08:16:51 PDT 2025

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@@ -871,11 +871,11 @@ multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> {
 }
 
 class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
-                                RegisterClass addr_rc, string dns="">
+                                RegisterClass addr_rc, string dns="", bits<1> hasR128=false>
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mbrkusanin wrote:

```suggestion
                                RegisterClass addr_rc, string dns="", bit hasR128=false>
```

Here and below in other cases

https://github.com/llvm/llvm-project/pull/132264
