[llvm] [WIP][AMDGPU][MC] Allow 128-bit rsrc register in MIMG instructions (PR #132264)

[Mirko Brkušanin via llvm-commits]

https://github.com/mbrkusanin commented:

Should the following cases now fail to encode?
```
llvm-mc --arch=amdgcn -mcpu=tonga --show-encoding --show-inst <<< "image_atomic_add v5, v1, s[8:11] dmask:0x1"

llvm-mc --arch=amdgcn -mcpu=tonga --show-encoding --show-inst <<< "image_atomic_add v5, v1, s[8:15] dmask:0x1 r128"
```


https://github.com/llvm/llvm-project/pull/132264