[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

[Fabian Ritter via llvm-commits]

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@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress",  SDTPtrLeaf, [],
 
 def add        : SDNode<"ISD::ADD"       , SDTIntBinOp   ,
                         [SDNPCommutative, SDNPAssociative]>;
-def ptradd     : SDNode<"ISD::ADD"       , SDTPtrAddOp, []>;
+def ptradd     : SDNode<"ISD::PTRADD"    , SDTPtrAddOp, []>;
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ritter-x2a wrote:

The [AMDGPU ptradd line](https://github.com/llvm/llvm-project/blob/a481452cd88acc180f82dd5631257c8954ed7812/llvm/lib/Target/AMDGPU/VOP3Instructions.td#L751) has an effect for global ISel, it shouldn't be removed. This ptradd SDNode was introduced as an equivalent to global ISel's G_PTR_ADD (as declared in [SelectionDAGCompat.td](https://github.com/llvm/llvm-project/blob/a481452cd88acc180f82dd5631257c8954ed7812/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td#L63)), to specify SDAG patterns that are auto-translated to global ISel patterns.
As far as I'm aware, it doesn't matter for that if `ptradd` uses `ISD::ADD` or `ISD::PTRADD`, so changing it as the PR currently does is fine.

https://github.com/llvm/llvm-project/pull/105669