[llvm] a481452 - [RISCV] Add OR/XOR/SUB to RISCVInstrInfo::isCopyInstrImpl (#132002)
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Fri Mar 28 05:59:22 PDT 2025
Author: Alex Bradbury
Date: 2025-03-28T12:59:18Z
New Revision: a481452cd88acc180f82dd5631257c8954ed7812
URL: https://github.com/llvm/llvm-project/commit/a481452cd88acc180f82dd5631257c8954ed7812
DIFF: https://github.com/llvm/llvm-project/commit/a481452cd88acc180f82dd5631257c8954ed7812.diff
LOG: [RISCV] Add OR/XOR/SUB to RISCVInstrInfo::isCopyInstrImpl (#132002)
This adds coverage for additional instructions in isCopyInstrImpl, for
now picking just those where I can observe that there is a codegen
difference for SPEC.
This allows MachineCopyPropagation to successfully eliminate no-op moves in this form.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e9fa0c4e3bf35..47bb7e191b065 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1752,6 +1752,8 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
default:
break;
case RISCV::ADD:
+ case RISCV::OR:
+ case RISCV::XOR:
if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0 &&
MI.getOperand(2).isReg())
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
@@ -1765,6 +1767,11 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
MI.getOperand(2).getImm() == 0)
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
break;
+ case RISCV::SUB:
+ if (MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0 &&
+ MI.getOperand(1).isReg())
+ return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ break;
case RISCV::FSGNJ_D:
case RISCV::FSGNJ_S:
case RISCV::FSGNJ_H:
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index f7351f00ae282..ac802c8d33fa1 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -135,31 +135,50 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
EXPECT_EQ(MI4Res->Destination->getReg(), RISCV::F1_D);
EXPECT_EQ(MI4Res->Source->getReg(), RISCV::F2_D);
- // ADD.
- MachineInstr *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
- .addReg(RISCV::X2)
- .addReg(RISCV::X3)
- .getInstr();
- auto MI5Res = TII->isCopyInstrImpl(*MI5);
- EXPECT_FALSE(MI5Res.has_value());
+ // ADD/OR/XOR.
+ for (unsigned Opc : {RISCV::ADD, RISCV::OR, RISCV::XOR}) {
+ MachineInstr *MI5 = BuildMI(*MF, DL, TII->get(Opc), RISCV::X1)
+ .addReg(RISCV::X2)
+ .addReg(RISCV::X3)
+ .getInstr();
+ auto MI5Res = TII->isCopyInstrImpl(*MI5);
+ EXPECT_FALSE(MI5Res.has_value());
+
+ MachineInstr *MI6 = BuildMI(*MF, DL, TII->get(Opc), RISCV::X1)
+ .addReg(RISCV::X0)
+ .addReg(RISCV::X2)
+ .getInstr();
+ auto MI6Res = TII->isCopyInstrImpl(*MI6);
+ ASSERT_TRUE(MI6Res.has_value());
+ EXPECT_EQ(MI6Res->Destination->getReg(), RISCV::X1);
+ EXPECT_EQ(MI6Res->Source->getReg(), RISCV::X2);
+
+ MachineInstr *MI7 = BuildMI(*MF, DL, TII->get(Opc), RISCV::X1)
+ .addReg(RISCV::X2)
+ .addReg(RISCV::X0)
+ .getInstr();
+ auto MI7Res = TII->isCopyInstrImpl(*MI7);
+ ASSERT_TRUE(MI7Res.has_value());
+ EXPECT_EQ(MI7Res->Destination->getReg(), RISCV::X1);
+ EXPECT_EQ(MI7Res->Source->getReg(), RISCV::X2);
+ }
- MachineInstr *MI6 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
+ // SUB.
+ MachineInstr *MI8 = BuildMI(*MF, DL, TII->get(RISCV::SUB), RISCV::X1)
.addReg(RISCV::X0)
.addReg(RISCV::X2)
.getInstr();
- auto MI6Res = TII->isCopyInstrImpl(*MI6);
- ASSERT_TRUE(MI6Res.has_value());
- EXPECT_EQ(MI6Res->Destination->getReg(), RISCV::X1);
- EXPECT_EQ(MI6Res->Source->getReg(), RISCV::X2);
+ auto MI8Res = TII->isCopyInstrImpl(*MI8);
+ EXPECT_FALSE(MI8Res.has_value());
- MachineInstr *MI7 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
+ MachineInstr *MI9 = BuildMI(*MF, DL, TII->get(RISCV::SUB), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X0)
.getInstr();
- auto MI7Res = TII->isCopyInstrImpl(*MI7);
- ASSERT_TRUE(MI7Res.has_value());
- EXPECT_EQ(MI7Res->Destination->getReg(), RISCV::X1);
- EXPECT_EQ(MI7Res->Source->getReg(), RISCV::X2);
+ auto MI9Res = TII->isCopyInstrImpl(*MI9);
+ ASSERT_TRUE(MI9Res.has_value());
+ EXPECT_EQ(MI9Res->Destination->getReg(), RISCV::X1);
+ EXPECT_EQ(MI9Res->Source->getReg(), RISCV::X2);
}
TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
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