[llvm] [RISCV] Disable i1 fixed vectors with more than 1024 elements. (PR #133267)

[Craig Topper via llvm-commits]

topperc wrote:

> Can v2048i8 be added to make MVT symmetric?

To support RISC-V we would need to add any of these that are missing: v2048i8, v1024i16, v512i32, v256i64, v512i32, and v256f64.

https://github.com/llvm/llvm-project/pull/133267