[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Mallikarjuna Gouda via llvm-commits]

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@@ -996,8 +999,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
-  def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
-  def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
+  let hasNoSchedulingInfo = 1 in {
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mgoudar wrote:

addressed the changes.

https://github.com/llvm/llvm-project/pull/132704