[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)
Mallikarjuna Gouda via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 26 00:23:20 PDT 2025
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@@ -983,7 +983,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
- def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
+
+ let hasNoSchedulingInfo = 1 in {
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mgoudar wrote:
addressed the changes.
https://github.com/llvm/llvm-project/pull/132704
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