[llvm] Houngkoungting patch 1 (PR #132927)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-transforms

Author: 黃國庭 (houngkoungting)

<details>
<summary>Changes</summary>

[MachineCopyPropagation] Fix undefined physical register on SystemZ (#<!-- -->131478)
 
### Problem
Issue #<!-- -->131478 reports that the SystemZ backend encounters an "undefined physical register" error in the Machine Verifier after commit 2def1c4 ([RISCV][MCP] Remove redundant move from tail duplication, #<!-- -->89865). The commit relaxed the COPY instruction check in `BackwardCopyPropagateBlock` from `if (CopyOperands && MI.getNumOperands() == 2)` to `if (CopyOperands)` to support RISC-V optimizations (e.g., recognizing `%0 = ADDI %1, 0` as a COPY). However, this change caused SystemZ to misidentify non-standard instructions as COPYs, leading to their erroneous removal and undefined register usage.

Please let me know if changes are needed.

---
Full diff: https://github.com/llvm/llvm-project/pull/132927.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/MachineCopyPropagation.cpp (+17-3) 
- (modified) llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp (+1) 


``````````diff
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index ff75b87b23128..8b241469d4300 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -1201,9 +1201,23 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
     std::optional<DestSourcePair> CopyOperands =
         isCopyInstr(MI, *TII, UseCopyInstr);
     if (CopyOperands) {
-      Register DefReg = CopyOperands->Destination->getReg();
-      Register SrcReg = CopyOperands->Source->getReg();
-
+      bool isRISCV = (MBB.getParent()->getSubtarget().getTargetTriple().getArchName() == "riscv64" ||MBB.getParent()->getSubtarget().getTargetTriple().getArchName() == "riscv32");
+      Register DefReg;
+      Register SrcReg;
+      
+      if (isRISCV) { 
+        DefReg = CopyOperands->Destination->getReg();
+        SrcReg = CopyOperands->Source->getReg();
+        }
+       else { 
+        if (MI.getNumOperands() == 2) {   
+          DefReg = CopyOperands->Destination->getReg();
+          SrcReg = CopyOperands->Source->getReg();
+          
+         }
+       }
+
+      
       if (!TRI->regsOverlap(DefReg, SrcReg)) {
         // Unlike forward cp, we don't invoke propagateDefs here,
         // just let forward cp do COPY-to-COPY propagation.
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 90cd279e8a457..e73bd002b8dc0 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -994,6 +994,7 @@ static bool setShiftFlags(BinaryOperator &I, const SimplifyQuery &Q) {
       I.setIsExact();
       return true;
     }
+ 
   }
 
   // Compute what we know about shift count.

``````````

</details>


https://github.com/llvm/llvm-project/pull/132927