[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Min-Yih Hsu via llvm-commits]

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+//==- MipsScheduleI6400.td - I6400 Scheduling Definitions --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+def MipsI6400Model : SchedMachineModel {
+  int IssueWidth = 2;         // 2x dispatched per cycle
+  int MicroOpBufferSize = 48; // min(48, 48, 64)
+  int LoadLatency = 3;
+  int MispredictPenalty = 8;
+
+  let CompleteModel = 1;
+  let FullInstRWOverlapCheck = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasMips64r5, HasMips32r5,
+                                         InMicroMips, InMips16Mode, HasCnMips,
+					 HasCnMipsP,  HasDSP, HasDSPR2,
+					 HasMips3D, HasMT, HasCRC,
+					 NotMips32r6, NotMips64r6, HasEVA];
+}
+
+let SchedModel = MipsI6400Model in {
+
+  // AGEN Pipelines
+  // ==============
+  def I6400AGEN : ProcResource<1> { let BufferSize = 16; }
+  def I6400IssueLSU : ProcResource<1> { let Super = I6400AGEN; }
+  def I6400IssueALU1 : ProcResource<1> { let Super = I6400AGEN; }
+
+  def I6400WriteLSUStore : SchedWriteRes<[I6400IssueLSU]> { let Latency = 1; }
+  def I6400WriteLSUStore2 : SchedWriteRes<[I6400IssueLSU]> {
+    let Latency = 8;
+    let ReleaseAtCycles = [5];
+  }
+  def I6400WriteLSULoad : SchedWriteRes<[I6400IssueLSU]> { let Latency = 3; }
+  def I6400WriteLSUPref : SchedWriteRes<[I6400IssueLSU]> { let Latency = 1; }
+  def I6400WriteLSUOther : SchedWriteRes<[I6400IssueLSU]> {
+    let Latency = 6;
+    let ReleaseAtCycles = [5];
+  }
+
+  // LSU pipelines
+  // =============
+  def : InstRW<[I6400WriteLSUStore], (instrs SB, SD, SH, SW, SDC1, SDC164, SWC1, SWC2_R6,
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mshockwave wrote:

Is it possible avoid using `SchedWriteRes` + `InstRW` and using the normal `SchedWrite` + `WriteRes` instead?

`InstRW` really should be used for "ad-hoc fixing" nowadays (e.g. instruction A & B share the same scheduling class in their instruction definitions, but they should be in two different scheduling classes in your core)

https://github.com/llvm/llvm-project/pull/132704