[llvm] [AMDGPU] 4-align TTMP triples (PR #132759)

[Jay Foad via llvm-commits]

jayfoad wrote:

> > There is no hardware use for them. To quote the (RDNA4) ISA doc, "Quad-alignment of SGPRs is required for operations on more than 64-bits".
> 
> Yes, there is no hardware use. But we can do an unaligned copy from a real value to a synthetic unaligned class and potentially avoid a spill

I see. I'm not thrilled about the idea of creating artificial register classes like TTMP_96_Unaligned just for the benefit of artificial instructions like S_MOV_B96_pseudo. It seems like there should be a better way.

https://github.com/llvm/llvm-project/pull/132759