[llvm] d536d13 - [X86] x86-64-double-shifts-var.ll - regenerate with update_llc_test_checks script to show full codegen

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-03-24T11:38:34Z
New Revision: d536d134276f667881917c9d3a32dcdeff683560

URL: https://github.com/llvm/llvm-project/commit/d536d134276f667881917c9d3a32dcdeff683560
DIFF: https://github.com/llvm/llvm-project/commit/d536d134276f667881917c9d3a32dcdeff683560.diff

LOG: [X86] x86-64-double-shifts-var.ll - regenerate with update_llc_test_checks script to show full codegen

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
index bbaa414924707..58f6a66aeff79 100644
--- a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -1,22 +1,23 @@
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-fx | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8-sse3 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron-sse3 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64-sse3 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=amdfam10 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-fx | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8-sse3 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron-sse3 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64-sse3 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=amdfam10 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=BMI
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s --check-prefixes=BMI
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=BMI
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s --check-prefixes=BMI
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s --check-prefixes=BMI2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=BMI2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=BMI2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=BMI2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=BMI2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=BMI2
 
 ; Verify that for the X86_64 processors that are known to have poor latency
 ; double precision shift instructions we do not generate 'shld' or 'shrd'
@@ -28,8 +29,40 @@
 ;}
 
 define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
+; X64-LABEL: lshift:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movl %edx, %ecx
+; X64-NEXT:    movq %rsi, %rax
+; X64-NEXT:    shlq %cl, %rdi
+; X64-NEXT:    shrq %rax
+; X64-NEXT:    notb %cl
+; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-NEXT:    shrq %cl, %rax
+; X64-NEXT:    orq %rdi, %rax
+; X64-NEXT:    retq
+;
+; BMI-LABEL: lshift:
+; BMI:       # %bb.0: # %entry
+; BMI-NEXT:    movq %rsi, %rax
+; BMI-NEXT:    movl %edx, %ecx
+; BMI-NEXT:    shrq %rax
+; BMI-NEXT:    shlq %cl, %rdi
+; BMI-NEXT:    notb %cl
+; BMI-NEXT:    # kill: def $cl killed $cl killed $ecx
+; BMI-NEXT:    shrq %cl, %rax
+; BMI-NEXT:    orq %rdi, %rax
+; BMI-NEXT:    retq
+;
+; BMI2-LABEL: lshift:
+; BMI2:       # %bb.0: # %entry
+; BMI2-NEXT:    # kill: def $edx killed $edx def $rdx
+; BMI2-NEXT:    shlxq %rdx, %rdi, %rcx
+; BMI2-NEXT:    notb %dl
+; BMI2-NEXT:    shrq %rsi
+; BMI2-NEXT:    shrxq %rdx, %rsi, %rax
+; BMI2-NEXT:    orq %rcx, %rax
+; BMI2-NEXT:    retq
 entry:
-; CHECK-NOT: shld
   %sh_prom = zext i32 %c to i64
   %shl = shl i64 %a, %sh_prom
   %sub = sub nsw i32 64, %c
@@ -45,8 +78,38 @@ entry:
 ;}
 
 define i64 @rshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
+; X64-LABEL: rshift:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movl %edx, %ecx
+; X64-NEXT:    shrq %cl, %rdi
+; X64-NEXT:    leaq (%rsi,%rsi), %rax
+; X64-NEXT:    notb %cl
+; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-NEXT:    shlq %cl, %rax
+; X64-NEXT:    orq %rdi, %rax
+; X64-NEXT:    retq
+;
+; BMI-LABEL: rshift:
+; BMI:       # %bb.0: # %entry
+; BMI-NEXT:    movl %edx, %ecx
+; BMI-NEXT:    leaq (%rsi,%rsi), %rax
+; BMI-NEXT:    shrq %cl, %rdi
+; BMI-NEXT:    notb %cl
+; BMI-NEXT:    # kill: def $cl killed $cl killed $ecx
+; BMI-NEXT:    shlq %cl, %rax
+; BMI-NEXT:    orq %rdi, %rax
+; BMI-NEXT:    retq
+;
+; BMI2-LABEL: rshift:
+; BMI2:       # %bb.0: # %entry
+; BMI2-NEXT:    # kill: def $edx killed $edx def $rdx
+; BMI2-NEXT:    shrxq %rdx, %rdi, %rcx
+; BMI2-NEXT:    notb %dl
+; BMI2-NEXT:    addq %rsi, %rsi
+; BMI2-NEXT:    shlxq %rdx, %rsi, %rax
+; BMI2-NEXT:    orq %rcx, %rax
+; BMI2-NEXT:    retq
 entry:
-; CHECK-NOT: shrd
   %sh_prom = zext i32 %c to i64
   %shr = lshr i64 %a, %sh_prom
   %sub = sub nsw i32 64, %c