[llvm] Add RISC-V support information to readme (PR #132699)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tools-llvm-exegesis

Author: None (AnastasiyaChernikova)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/132699.diff


1 Files Affected:

- (modified) llvm/tools/llvm-exegesis/README.md (+2) 


``````````diff
diff --git a/llvm/tools/llvm-exegesis/README.md b/llvm/tools/llvm-exegesis/README.md
index deb0f230f032f..b58a9bcaa2cf2 100644
--- a/llvm/tools/llvm-exegesis/README.md
+++ b/llvm/tools/llvm-exegesis/README.md
@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISCV
+  * Supported extensions: compressed, atomic, multiply-divide, initual vector instructions.
 
 Note that not all benchmarking functionality is guaranteed to work on all platforms.
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/132699