[llvm] Add RISC-V support information to readme (PR #132699)

[via llvm-commits]

https://github.com/AnastasiyaChernikova updated https://github.com/llvm/llvm-project/pull/132699

>From 3f16a992929b28acf588edf97270bc26326332b9 Mon Sep 17 00:00:00 2001
From: Anastasiya Chernikova <anastasiya.chernikova at syntacore.com>
Date: Mon, 24 Mar 2025 12:34:27 +0300
Subject: [PATCH] Add RISC-V support information to readme

---
 llvm/tools/llvm-exegesis/README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/tools/llvm-exegesis/README.md b/llvm/tools/llvm-exegesis/README.md
index deb0f230f032f..b58a9bcaa2cf2 100644
--- a/llvm/tools/llvm-exegesis/README.md
+++ b/llvm/tools/llvm-exegesis/README.md
@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISCV
+  * Supported extensions: compressed, atomic, multiply-divide, initual vector instructions.
 
 Note that not all benchmarking functionality is guaranteed to work on all platforms.