[llvm] [AMDGPU][GlobalISel] Enable vector reductions (PR #131413)

[Matt Arsenault via llvm-commits]

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@@ -343,6 +343,8 @@ inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
   return isKnownNeverNaN(Val, MRI, true);
 }
 
+bool isKnownNeverZeroFloat(Register Val, const MachineRegisterInfo &MRI);
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arsenm wrote:

For this, I was planning on renaming GISelKnownBits to GISelValueTracking, and just start with the generalized computeKnownFPClass. The DAG has much weaker versions of all of these functions, we're better off copying the IR pattern 

https://github.com/llvm/llvm-project/pull/131413