[llvm] [AMDGPU][GlobalISel] Enable vector reductions (PR #131413)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff 5265412c13b4581e55e5d419f39a2206139b30c6 b9b659cc45196ed76bed6abff4ad27f4d74b1ae2 --extensions cpp,h -- llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h llvm/include/llvm/CodeGen/GlobalISel/Utils.h llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/Utils.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
``````````

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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index b20a79a24d..efa5dd062e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -8178,7 +8178,8 @@ LegalizerHelper::lowerFMinimum_FMaximum(MachineInstr &MI) {
   bool IsMax = Opc == TargetOpcode::G_FMAXIMUM;
 
   Register MinMax;
-  unsigned CompOpcIeee = IsMax ? TargetOpcode::G_FMAXNUM_IEEE : TargetOpcode::G_FMINNUM_IEEE;
+  unsigned CompOpcIeee =
+      IsMax ? TargetOpcode::G_FMAXNUM_IEEE : TargetOpcode::G_FMINNUM_IEEE;
   unsigned CompOpc = IsMax ? TargetOpcode::G_FMAXNUM : TargetOpcode::G_FMINNUM;
   CmpInst::Predicate CompPred = IsMax ? CmpInst::FCMP_OGT : CmpInst::FCMP_OLT;
   LLT S1 = LLT::scalar(1);
@@ -8194,13 +8195,15 @@ LegalizerHelper::lowerFMinimum_FMaximum(MachineInstr &MI) {
   } else {
     // NaN (if exists) will be propagated later, so orderness doesn't matter.
     auto Comp = MIRBuilder.buildFCmp(CompPred, S1, Src0, Src1);
-    MinMax = MIRBuilder.buildSelect(Ty, Comp,Src0, Src1).getReg(0);
+    MinMax = MIRBuilder.buildSelect(Ty, Comp, Src0, Src1).getReg(0);
   }
 
   // Propagate any NaN of both operands
-  if (!MI.getFlag(MachineInstr::FmNoNans) && (!isKnownNeverNaN(Src0, MRI) || !isKnownNeverNaN(Src1, MRI))) {
+  if (!MI.getFlag(MachineInstr::FmNoNans) &&
+      (!isKnownNeverNaN(Src0, MRI) || !isKnownNeverNaN(Src1, MRI))) {
     auto FPNaN = MIRBuilder.buildFConstant(Ty, APFloat::getNaN(FPSem));
-    auto Comp = MIRBuilder.buildFCmp(CmpInst::Predicate::FCMP_UNO, S1, Src0, Src1);
+    auto Comp =
+        MIRBuilder.buildFCmp(CmpInst::Predicate::FCMP_UNO, S1, Src0, Src1);
     MinMax = MIRBuilder.buildSelect(Ty, Comp, FPNaN, MinMax).getReg(0);
   }
 
@@ -8208,13 +8211,14 @@ LegalizerHelper::lowerFMinimum_FMaximum(MachineInstr &MI) {
   if (!MinMaxMustRespectOrderedZero && !MI.getFlag(MachineInstr::FmNsz) &&
       !isKnownNeverZeroFloat(Src0, MRI) && !isKnownNeverZeroFloat(Src1, MRI)) {
     auto Zero = MIRBuilder.buildFConstant(Ty, APFloat::getZero(FPSem));
-    auto IsZero = MIRBuilder.buildFCmp(CmpInst::Predicate::FCMP_OEQ, S1,MinMax, Zero);
+    auto IsZero =
+        MIRBuilder.buildFCmp(CmpInst::Predicate::FCMP_OEQ, S1, MinMax, Zero);
 
     unsigned TestZeroMask = IsMax ? fcPosZero : fcNegZero;
-    
+
     auto Src0Zero = MIRBuilder.buildIsFPClass(S1, Src0, TestZeroMask);
     auto Src0Comp = MIRBuilder.buildSelect(Ty, Src0Zero, Src0, MinMax);
-    
+
     auto Src1Zero = MIRBuilder.buildIsFPClass(S1, Src1, TestZeroMask);
     auto Src1Comp = MIRBuilder.buildSelect(Ty, Src1Zero, Src1, Src0Comp);
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index fc2d4954df..f36bd70409 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2112,13 +2112,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   getActionDefinitionsBuilder(G_PREFETCH).alwaysLegal();
 
   getActionDefinitionsBuilder(
-    {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,
-     G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,
-     G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,
-     G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
-    .legalFor(AllVectors)  
-    .scalarize(1)
-    .lower();
+      {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,
+       G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,
+       G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,
+       G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
+      .legalFor(AllVectors)
+      .scalarize(1)
+      .lower();
 
   getLegacyLegalizerInfo().computeTables();
   verify(*ST.getInstrInfo());

``````````

</details>


https://github.com/llvm/llvm-project/pull/131413