[llvm] [RISCV] Set AllocationPriority in line with LMUL (PR #131176)

[Philip Reames via llvm-commits]

================
@@ -752,18 +752,24 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
 
 def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>;
 
+let AllocationPriority = 2 in
----------------
preames wrote:

Doing this revealed that I hadn't handled the segment tuple register classes.  I decided to treat those as having the same priority as their lmul component; that is, I ignored NF.  There might be a better heuristic here.  

https://github.com/llvm/llvm-project/pull/131176