[llvm] [RISCV] Add implicit operand {VL, VTYPE} in RISCVInsertVSETVLI when u… (PR #130733)

[Pengcheng Wang via llvm-commits]

================
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
----------------
wangpc-pp wrote:

The `%1` and `type` issues are not addressed.

https://github.com/llvm/llvm-project/pull/130733