[llvm] [RISCV] Add implicit operand {VL, VTYPE} in RISCVInsertVSETVLI when u… (PR #130733)

[Hank Chang via llvm-commits]

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@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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HankChang736 wrote:

@wangpc-pp  I just created a precommit that contains original test case. Please check it out.

https://github.com/llvm/llvm-project/pull/130733