[llvm] [RISCV] Move let statement for hasSideEffects, mayLoad, mayStore into BranchCC_rri. NFC (PR #130721)
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Mon Mar 10 22:53:00 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
This is consistent with the isBranch and isTerminator flags already in the class.
Addresses feedback given on #<!-- -->130714 where I copied the inconsistent split into RISCVInstrInfoXCV.td.
---
Full diff: https://github.com/llvm/llvm-project/pull/130721.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+3-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5ce826b136832..aab368680e814 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -523,7 +523,6 @@ include "RISCVInstrFormats.td"
// Instruction Class Templates
//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class BranchCC_rri<bits<3> funct3, string opcodestr>
: RVInstB<funct3, OPC_BRANCH, (outs),
(ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
@@ -531,6 +530,9 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
Sched<[WriteJmp, ReadJmp, ReadJmp]> {
let isBranch = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
+ let mayLoad = 0;
+ let mayStore = 0;
}
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
``````````
</details>
https://github.com/llvm/llvm-project/pull/130721
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