[llvm] [RISCV] Move let statement for hasSideEffects, mayLoad, mayStore into BranchCC_rri. NFC (PR #130721)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/130721

This is consistent with the isBranch and isTerminator flags already in the class.

Addresses feedback given on #130714 where I copied the inconsistent split into RISCVInstrInfoXCV.td.

>From 03edd2c07b4e27f33320459f2b61dd27be6d3e00 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 10 Mar 2025 22:45:58 -0700
Subject: [PATCH] [RISCV] Move let statement for hasSideEffects, mayLoad,
 mayStore into BranchCC_rri. NFC

This is consistent with the isBranch and isTerminator flags already
in the class.

Addresses feedback given on #130714 where I did the same inconsistent
split in RISCVInstrInfoXCV.td.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5ce826b136832..aab368680e814 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -523,7 +523,6 @@ include "RISCVInstrFormats.td"
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class BranchCC_rri<bits<3> funct3, string opcodestr>
     : RVInstB<funct3, OPC_BRANCH, (outs),
               (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
@@ -531,6 +530,9 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
       Sched<[WriteJmp, ReadJmp, ReadJmp]> {
   let isBranch = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {