[llvm] 7fb71d1 - [RISCV][test] Add test case showing case where machine copy propagation leaves behind a no-op reg move

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2025-03-10T12:53:55Z
New Revision: 7fb71d151127a30d7299336511cbcc06601047b9

URL: https://github.com/llvm/llvm-project/commit/7fb71d151127a30d7299336511cbcc06601047b9
DIFF: https://github.com/llvm/llvm-project/commit/7fb71d151127a30d7299336511cbcc06601047b9.diff

LOG: [RISCV][test] Add test case showing case where machine copy propagation leaves behind a no-op reg move

Pre-commit for #129889.

Added: 
    llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir b/llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir
new file mode 100644
index 0000000000000..0ddd7d8bfc12a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -o - %s -mtriple=riscv64 -run-pass=machine-cp -mcp-use-is-copy-instr | FileCheck %s
+
+## This test was added to capture a case where MachineCopyPropagation risks
+## leaving a no-op register move (add, x0, reg).
+## FIXME: No-op register move is left behind after machine-cp.
+
+---
+name: ham
+body: |
+  ; CHECK-LABEL: name: ham
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $x11 = ANDI killed renamable $x10, 1
+  ; CHECK-NEXT:   renamable $x10 = ADDI $x0, 1
+  ; CHECK-NEXT:   BEQ killed renamable $x11, $x0, %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $x11 = ADDI $x0, 0
+  ; CHECK-NEXT:   renamable $x10 = ADD $x0, killed renamable $x10
+  ; CHECK-NEXT:   BEQ renamable $x10, $x0, %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $x10 = ADDI $x0, 0
+  ; CHECK-NEXT:   PseudoRET implicit $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $x11 = ADDI $x0, 1
+  ; CHECK-NEXT:   renamable $x10 = ADD killed renamable $x11, killed renamable $x10
+  ; CHECK-NEXT:   BNE renamable $x10, $x0, %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoRET implicit $x10
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $x10
+
+    renamable $x11 = ANDI killed renamable $x10, 1
+    renamable $x10 = ADDI $x0, 1
+    BEQ killed renamable $x11, $x0, %bb.2
+
+  bb.1:
+    successors: %bb.4(0x40000000), %bb.5(0x40000000)
+    liveins: $x10
+
+    $x11 = ADDI $x0, 0
+    renamable $x10 = ADD killed renamable $x11, killed renamable $x10
+    BEQ renamable $x10, $x0, %bb.4
+
+  bb.5:
+    $x10 = ADDI $x0, 0
+    PseudoRET implicit $x10
+
+  bb.2:
+    successors: %bb.4(0x40000000), %bb.5(0x40000000)
+    liveins: $x10
+
+    renamable $x11 = ADDI $x0, 1
+    renamable $x10 = ADD killed renamable $x11, killed renamable $x10
+    BNE renamable $x10, $x0, %bb.5
+
+  bb.4:
+    liveins: $x10
+
+    PseudoRET implicit $x10
+...