[llvm] [CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (PR #129690)
Vikram Hegde via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 9 23:14:37 PDT 2025
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/129690
>From 4ccbc3864a3ab6cdf12ba68b462d5a47e2efe996 Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Tue, 4 Mar 2025 15:41:00 +0530
Subject: [PATCH 1/3] [CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM
---
llvm/include/llvm/CodeGen/PostRAMachineSink.h | 30 +++++++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/MachineSink.cpp | 79 ++++++++++++-------
llvm/lib/Passes/PassBuilder.cpp | 1 +
.../AArch64/bisect-post-ra-machine-sink.mir | 2 +
.../CodeGen/AArch64/post-ra-machine-sink.mir | 1 +
.../CodeGen/AMDGPU/postra-machine-sink.mir | 1 +
.../AMDGPU/postra-sink-update-dependency.mir | 1 +
.../AMDGPU/sink-after-control-flow-postra.mir | 1 +
llvm/test/CodeGen/SystemZ/no-postra-sink.mir | 1 +
.../CodeGen/X86/postra-ignore-dbg-instrs.mir | 1 +
llvm/test/CodeGen/X86/pr38952.mir | 1 +
.../DebugInfo/MIR/X86/postra-subreg-sink.mir | 1 +
16 files changed, 96 insertions(+), 31 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/PostRAMachineSink.h
diff --git a/llvm/include/llvm/CodeGen/PostRAMachineSink.h b/llvm/include/llvm/CodeGen/PostRAMachineSink.h
new file mode 100644
index 0000000000000..2f1f79a0480df
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/PostRAMachineSink.h
@@ -0,0 +1,30 @@
+//===- llvm/CodeGen/PostRAMachineSink.h -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_POSTRAMACHINESINK_H
+#define LLVM_CODEGEN_POSTRAMACHINESINK_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class PostRAMachineSinkingPass
+ : public PassInfoMixin<PostRAMachineSinkingPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoVRegs);
+ }
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_POSTRAMACHINESINK_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index c2cb4cb4ef477..8b01a74ddc835 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -238,7 +238,7 @@ void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
void initializePostMachineSchedulerLegacyPass(PassRegistry &);
void initializePostRAHazardRecognizerPass(PassRegistry &);
-void initializePostRAMachineSinkingPass(PassRegistry &);
+void initializePostRAMachineSinkingLegacyPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
void initializePreISelIntrinsicLoweringLegacyPassPass(PassRegistry &);
void initializePrintFunctionPassWrapperPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 25899d04dc664..960072d26a7c0 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -59,6 +59,7 @@
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PeepholeOptimizer.h"
+#include "llvm/CodeGen/PostRAMachineSink.h"
#include "llvm/CodeGen/PostRASchedulerList.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index f99a5f2c74bf3..9fcb6b6cede15 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -154,6 +154,7 @@ MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
+MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass())
MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("post-ra-pseudos", ExpandPostRAPseudosPass())
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
@@ -271,7 +272,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPa
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
-DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index beb7fb284a376..2931bf0951c6b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -107,7 +107,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePeepholeOptimizerLegacyPass(Registry);
initializePostMachineSchedulerLegacyPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
- initializePostRAMachineSinkingPass(Registry);
+ initializePostRAMachineSinkingLegacyPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 173193bb6266c..737d7d2f5d0db 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -43,6 +43,7 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSizeOpts.h"
+#include "llvm/CodeGen/PostRAMachineSink.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/SlotIndexes.h"
@@ -2068,12 +2069,31 @@ void MachineSinking::SalvageUnsunkDebugUsersOfCopy(
//===----------------------------------------------------------------------===//
namespace {
-class PostRAMachineSinking : public MachineFunctionPass {
+class PostRAMachineSinkingImpl {
+ /// Track which register units have been modified and used.
+ LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+
+ /// Track DBG_VALUEs of (unmodified) register units. Each DBG_VALUE has an
+ /// entry in this map for each unit it touches. The DBG_VALUE's entry
+ /// consists of a pointer to the instruction itself, and a vector of registers
+ /// referred to by the instruction that overlap the key register unit.
+ DenseMap<MCRegUnit, SmallVector<MIRegs, 2>> SeenDbgInstrs;
+
+ /// Sink Copy instructions unused in the same block close to their uses in
+ /// successors.
+ bool tryToSinkCopy(MachineBasicBlock &BB, MachineFunction &MF,
+ const TargetRegisterInfo *TRI, const TargetInstrInfo *TII);
+
+public:
+ bool run(MachineFunction &MF);
+};
+
+class PostRAMachineSinkingLegacy : public MachineFunctionPass {
public:
bool runOnMachineFunction(MachineFunction &MF) override;
static char ID;
- PostRAMachineSinking() : MachineFunctionPass(ID) {}
+ PostRAMachineSinkingLegacy() : MachineFunctionPass(ID) {}
StringRef getPassName() const override { return "PostRA Machine Sink"; }
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -2085,28 +2105,14 @@ class PostRAMachineSinking : public MachineFunctionPass {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
}
-
-private:
- /// Track which register units have been modified and used.
- LiveRegUnits ModifiedRegUnits, UsedRegUnits;
-
- /// Track DBG_VALUEs of (unmodified) register units. Each DBG_VALUE has an
- /// entry in this map for each unit it touches. The DBG_VALUE's entry
- /// consists of a pointer to the instruction itself, and a vector of registers
- /// referred to by the instruction that overlap the key register unit.
- DenseMap<MCRegUnit, SmallVector<MIRegs, 2>> SeenDbgInstrs;
-
- /// Sink Copy instructions unused in the same block close to their uses in
- /// successors.
- bool tryToSinkCopy(MachineBasicBlock &BB, MachineFunction &MF,
- const TargetRegisterInfo *TRI, const TargetInstrInfo *TII);
};
+
} // namespace
-char PostRAMachineSinking::ID = 0;
-char &llvm::PostRAMachineSinkingID = PostRAMachineSinking::ID;
+char PostRAMachineSinkingLegacy::ID = 0;
+char &llvm::PostRAMachineSinkingID = PostRAMachineSinkingLegacy::ID;
-INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink",
+INITIALIZE_PASS(PostRAMachineSinkingLegacy, "postra-machine-sink",
"PostRA Machine Sink", false, false)
static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, Register Reg,
@@ -2227,10 +2233,10 @@ static bool hasRegisterDependency(MachineInstr *MI,
return HasRegDependency;
}
-bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
- MachineFunction &MF,
- const TargetRegisterInfo *TRI,
- const TargetInstrInfo *TII) {
+bool PostRAMachineSinkingImpl::tryToSinkCopy(MachineBasicBlock &CurBB,
+ MachineFunction &MF,
+ const TargetRegisterInfo *TRI,
+ const TargetInstrInfo *TII) {
SmallPtrSet<MachineBasicBlock *, 2> SinkableBBs;
// FIXME: For now, we sink only to a successor which has a single predecessor
// so that we can directly sink COPY instructions to the successor without
@@ -2356,10 +2362,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
return Changed;
}
-bool PostRAMachineSinking::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
+bool PostRAMachineSinkingImpl::run(MachineFunction &MF) {
bool Changed = false;
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
@@ -2371,3 +2374,23 @@ bool PostRAMachineSinking::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+
+bool PostRAMachineSinkingLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+
+ return PostRAMachineSinkingImpl().run(MF);
+}
+
+PreservedAnalyses
+PostRAMachineSinkingPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ if (!PostRAMachineSinkingImpl().run(MF))
+ return PreservedAnalyses::all();
+
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 8080059f0bb03..0b5902bcc6740 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -130,6 +130,7 @@
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PeepholeOptimizer.h"
+#include "llvm/CodeGen/PostRAMachineSink.h"
#include "llvm/CodeGen/PostRASchedulerList.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
diff --git a/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir b/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
index 15c1ccb0e609b..cf148f77b206b 100644
--- a/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
+++ b/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
@@ -1,5 +1,7 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck -check-prefix=RUN-POSTRA %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='postra-machine-sink' -o - %s | FileCheck -check-prefix=RUN-POSTRA %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=postra-machine-sink -opt-bisect-limit=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=BISECT-NO-RUN-POSTRA %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='postra-machine-sink' -opt-bisect-limit=0 -o - %s | FileCheck -check-prefix=BISECT-NO-RUN-POSTRA %s
---
diff --git a/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir b/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
index a0eb3c1979391..8394bc3d0702b 100644
--- a/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
+++ b/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='postra-machine-sink' -o - %s | FileCheck %s
---
# Sink w19 to %bb.1.
diff --git a/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir b/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
index 86863c3175364..987c5a2baf66a 100644
--- a/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
+++ b/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes='postra-machine-sink' -o - %s | FileCheck %s
# Don't sink copy that writes sub-register of another copy source register
# CHECK-LABEL: name: donotsinkcopy
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir b/llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
index 14617e066f954..8687d6ca4378f 100644
--- a/llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
+++ b/llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes='postra-machine-sink' -o - %s | FileCheck %s
#
# In the example, the ` $sgpr4 = COPY $sgpr2` was incorrectly sunk into bb.3. This happened because we did not update
# register uses when we found that `$sgpr2 = COPY $sgpr3` should not be sunk because of conflict with the successor's
diff --git a/llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir b/llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
index ff87c28bb7ec5..d134f290aa5f5 100644
--- a/llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
+++ b/llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=postra-machine-sink -mattr=+wavefrontsize64 -o - %s | FileCheck -check-prefixes=GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes='postra-machine-sink' -mattr=+wavefrontsize64 -o - %s | FileCheck -check-prefixes=GFX10 %s
# Ensure that PostRA Machine Sink does not sink instructions
# past block prologues which would overwrite their uses.
diff --git a/llvm/test/CodeGen/SystemZ/no-postra-sink.mir b/llvm/test/CodeGen/SystemZ/no-postra-sink.mir
index 0db431535c051..b358ca5c6e56b 100644
--- a/llvm/test/CodeGen/SystemZ/no-postra-sink.mir
+++ b/llvm/test/CodeGen/SystemZ/no-postra-sink.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -passes='postra-machine-sink' -o - %s | FileCheck %s
---
# Don't sink COPY to bb.2 since SLLK define r13l that is aliased with r12q.
diff --git a/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir b/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
index 7e37415463f45..c7e2e28228029 100644
--- a/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
+++ b/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=x86_64-none-linux-gnu -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-none-linux-gnu -passes=postra-machine-sink -o - %s | FileCheck %s
#
# This test was originally generated from the following sample:
#
diff --git a/llvm/test/CodeGen/X86/pr38952.mir b/llvm/test/CodeGen/X86/pr38952.mir
index d67174aa4847c..1d18738cf4ad4 100644
--- a/llvm/test/CodeGen/X86/pr38952.mir
+++ b/llvm/test/CodeGen/X86/pr38952.mir
@@ -1,4 +1,5 @@
# RUN: llc %s -run-pass=postra-machine-sink -o - | FileCheck %s
+# RUN: llc %s -passes='postra-machine-sink' -o - | FileCheck %s
--- |
; Module stripped of everything, MIR below is what's interesting
; ModuleID = '<stdin>'
diff --git a/llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir b/llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
index 2307df9b392ba..b54f93edfc492 100644
--- a/llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
+++ b/llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=x86_64-unknown-unknown %s -run-pass=postra-machine-sink -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-unknown-unknown %s -passes='postra-machine-sink' -o - | FileCheck %s
# Test that when we run the postra machine sinker (which sinks COPYs), that
# DBG_VALUEs of both sub and super-registers that depend on such COPYs are
# sunk with them.
>From 5e8b9494ba1b04c152d625aa2961281d5f95b7b3 Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Wed, 5 Mar 2025 11:22:57 +0530
Subject: [PATCH 2/3] chain preserveAnalysis calls
---
llvm/lib/CodeGen/MachineSink.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 737d7d2f5d0db..9af6de8cde74d 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -2390,7 +2390,5 @@ PostRAMachineSinkingPass::run(MachineFunction &MF,
if (!PostRAMachineSinkingImpl().run(MF))
return PreservedAnalyses::all();
- auto PA = getMachineFunctionPassPreservedAnalyses();
- PA.preserveSet<CFGAnalyses>();
- return PA;
+ return getMachineFunctionPassPreservedAnalyses().preserveSet<CFGAnalyses>();
}
>From efd8b50bb96573b150f25aa48e6244f40dd3e1df Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Mon, 10 Mar 2025 11:43:10 +0530
Subject: [PATCH 3/3] keep temp variable for preservedAnalyses
---
llvm/lib/CodeGen/MachineSink.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 9af6de8cde74d..dec9df17da066 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -2390,5 +2390,7 @@ PostRAMachineSinkingPass::run(MachineFunction &MF,
if (!PostRAMachineSinkingImpl().run(MF))
return PreservedAnalyses::all();
- return getMachineFunctionPassPreservedAnalyses().preserveSet<CFGAnalyses>();
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
}
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