[llvm] [RISCV] Use vmv.v.x for any rv32 e64 splat with equal halves (PR #130530)

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github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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git-clang-format --diff bac490b0bc9e870d479564334db14303043e6c83 1f06368d85d7b82437782d4c8ad8341393b06209 --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 27a4bbce1f..75ca98c926 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4369,8 +4369,7 @@ static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru,
         NewVL = DAG.getNode(ISD::ADD, DL, VL.getValueType(), VL, VL);
       else
         NewVL = DAG.getRegister(RISCV::X0, MVT::i32);
-      MVT InterVT =
-          MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2);
+      MVT InterVT = MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2);
       auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT,
                                   DAG.getUNDEF(InterVT), Lo, NewVL);
       return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);

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https://github.com/llvm/llvm-project/pull/130530