[llvm] 275d717 - [ARM] Use Register in FastISel. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 8 22:06:40 PST 2025
Author: Craig Topper
Date: 2025-03-08T21:58:35-08:00
New Revision: 275d7175aceffcc7d5c0827118a1dea6ebf85798
URL: https://github.com/llvm/llvm-project/commit/275d7175aceffcc7d5c0827118a1dea6ebf85798
DIFF: https://github.com/llvm/llvm-project/commit/275d7175aceffcc7d5c0827118a1dea6ebf85798.diff
LOG: [ARM] Use Register in FastISel. NFC
Added:
Modified:
llvm/lib/Target/ARM/ARMFastISel.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index eb7f196be4f1f..7c84766f4e780 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -132,17 +132,16 @@ class ARMFastISel final : public FastISel {
private:
// Code from FastISel.cpp.
- unsigned fastEmitInst_r(unsigned MachineInstOpcode,
- const TargetRegisterClass *RC, unsigned Op0);
- unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
- const TargetRegisterClass *RC,
- unsigned Op0, unsigned Op1);
- unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
- const TargetRegisterClass *RC,
- unsigned Op0, uint64_t Imm);
- unsigned fastEmitInst_i(unsigned MachineInstOpcode,
- const TargetRegisterClass *RC,
- uint64_t Imm);
+ Register fastEmitInst_r(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC, Register Op0);
+ Register fastEmitInst_rr(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC, Register Op0,
+ Register Op1);
+ Register fastEmitInst_ri(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC, Register Op0,
+ uint64_t Imm);
+ Register fastEmitInst_i(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC, uint64_t Imm);
// Backend specific FastISel code.
@@ -188,21 +187,21 @@ class ARMFastISel final : public FastISel {
bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
MaybeAlign Alignment = std::nullopt, bool isZExt = true,
bool allocReg = true);
- bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
+ bool ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
MaybeAlign Alignment = std::nullopt);
bool ARMComputeAddress(const Value *Obj, Address &Addr);
void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
bool ARMIsMemCpySmall(uint64_t Len);
bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
MaybeAlign Alignment);
- unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
- unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
- unsigned ARMMaterializeInt(const Constant *C, MVT VT);
- unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
- unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
- unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
+ Register ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
+ Register ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
+ Register ARMMaterializeInt(const Constant *C, MVT VT);
+ Register ARMMaterializeGV(const GlobalValue *GV, MVT VT);
+ Register ARMMoveToFPReg(MVT VT, Register SrcReg);
+ Register ARMMoveToIntReg(MVT VT, Register SrcReg);
unsigned ARMSelectCallOp(bool UseReg);
- unsigned ARMLowerPICELF(const GlobalValue *GV, MVT VT);
+ Register ARMLowerPICELF(const GlobalValue *GV, MVT VT);
const TargetLowering *getTargetLowering() { return &TLI; }
@@ -219,7 +218,7 @@ class ARMFastISel final : public FastISel {
CallingConv::ID CC,
unsigned &NumBytes,
bool isVarArg);
- unsigned getLibcallReg(const Twine &Name);
+ Register getLibcallReg(const Twine &Name);
bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
const Instruction *I, CallingConv::ID CC,
unsigned &NumBytes, bool isVarArg);
@@ -291,9 +290,9 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
return MIB;
}
-unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
+Register ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
- unsigned Op0) {
+ Register Op0) {
Register ResultReg = createResultReg(RC);
const MCInstrDesc &II = TII.get(MachineInstOpcode);
@@ -313,9 +312,9 @@ unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
return ResultReg;
}
-unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
+Register ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
- unsigned Op0, unsigned Op1) {
+ Register Op0, Register Op1) {
Register ResultReg = createResultReg(RC);
const MCInstrDesc &II = TII.get(MachineInstOpcode);
@@ -340,9 +339,9 @@ unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
return ResultReg;
}
-unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
+Register ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
- unsigned Op0, uint64_t Imm) {
+ Register Op0, uint64_t Imm) {
Register ResultReg = createResultReg(RC);
const MCInstrDesc &II = TII.get(MachineInstOpcode);
@@ -365,7 +364,7 @@ unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
return ResultReg;
}
-unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
+Register ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
uint64_t Imm) {
Register ResultReg = createResultReg(RC);
@@ -386,8 +385,9 @@ unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
// TODO: Don't worry about 64-bit now, but when this is fixed remove the
// checks from the various callers.
-unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
- if (VT == MVT::f64) return 0;
+Register ARMFastISel::ARMMoveToFPReg(MVT VT, Register SrcReg) {
+ if (VT == MVT::f64)
+ return Register();
Register MoveReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
@@ -396,8 +396,9 @@ unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
return MoveReg;
}
-unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
- if (VT == MVT::i64) return 0;
+Register ARMFastISel::ARMMoveToIntReg(MVT VT, Register SrcReg) {
+ if (VT == MVT::i64)
+ return Register();
Register MoveReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
@@ -409,7 +410,7 @@ unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
// For double width floating point we need to materialize two constants
// (the high and the low) into integer registers then use a move to get
// the combined constant into an FP reg.
-unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
+Register ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
const APFloat Val = CFP->getValueAPF();
bool is64bit = VT == MVT::f64;
@@ -448,9 +449,9 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
return DestReg;
}
-unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
+Register ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
- return 0;
+ return Register();
// If we can do this in a single instruction without a constant pool entry
// do so now.
@@ -483,7 +484,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
}
}
- unsigned ResultReg = 0;
+ Register ResultReg;
if (Subtarget->useMovt())
ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
@@ -492,7 +493,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
// Load from constant pool. For now 32-bit only.
if (VT != MVT::i32)
- return 0;
+ return Register();
// MachineConstantPool wants an explicit alignment.
Align Alignment = DL.getPrefTypeAlign(C->getType());
@@ -517,13 +518,14 @@ bool ARMFastISel::isPositionIndependent() const {
return TLI.isPositionIndependent();
}
-unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
+Register ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
// For now 32-bit only.
- if (VT != MVT::i32 || GV->isThreadLocal()) return 0;
+ if (VT != MVT::i32 || GV->isThreadLocal())
+ return Register();
// ROPI/RWPI not currently supported.
if (Subtarget->isROPI() || Subtarget->isRWPI())
- return 0;
+ return Register();
bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
@@ -533,7 +535,8 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
// FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
bool IsThreadLocal = GVar && GVar->isThreadLocal();
- if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
+ if (!Subtarget->isTargetMachO() && IsThreadLocal)
+ return Register();
bool IsPositionIndependent = isPositionIndependent();
// Use movw+movt when possible, it avoids constant pool entries.
@@ -637,7 +640,7 @@ Register ARMFastISel::fastMaterializeConstant(const Constant *C) {
return Register();
}
-// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
+// TODO: Register ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
Register ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
// Don't handle dynamic allocas.
@@ -985,7 +988,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
// Create the base instruction, then add the operands.
if (allocReg)
ResultReg = createResultReg(RC);
- assert(ResultReg > 255 && "Expected an allocated virtual register.");
+ assert(ResultReg.isVirtual() && "Expected an allocated virtual register.");
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(Opc), ResultReg);
AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
@@ -1038,7 +1041,7 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
return true;
}
-bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
+bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
MaybeAlign Alignment) {
unsigned StrOpc;
bool useAM3 = false;
@@ -1135,7 +1138,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
bool ARMFastISel::SelectStore(const Instruction *I) {
Value *Op0 = I->getOperand(0);
- unsigned SrcReg = 0;
+ Register SrcReg;
// Atomic stores need special handling.
if (cast<StoreInst>(I)->isAtomic())
@@ -1163,7 +1166,8 @@ bool ARMFastISel::SelectStore(const Instruction *I) {
// Get the value to be stored into a register.
SrcReg = getRegForValue(Op0);
- if (SrcReg == 0) return false;
+ if (!SrcReg)
+ return false;
// See if we can handle this address.
Address Addr;
@@ -1289,7 +1293,8 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
}
Register CmpReg = getRegForValue(BI->getCondition());
- if (CmpReg == 0) return false;
+ if (!CmpReg)
+ return false;
// We've been divorced from our compare! Our block was split, and
// now our compare lives in a predecessor block. We musn't
@@ -1320,7 +1325,8 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
Register AddrReg = getRegForValue(I->getOperand(0));
- if (AddrReg == 0) return false;
+ if (!AddrReg)
+ return false;
unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
assert(isThumb2 || Subtarget->hasV4TOps());
@@ -1411,21 +1417,25 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
}
Register SrcReg1 = getRegForValue(Src1Value);
- if (SrcReg1 == 0) return false;
+ if (!SrcReg1)
+ return false;
- unsigned SrcReg2 = 0;
+ Register SrcReg2;
if (!UseImm) {
SrcReg2 = getRegForValue(Src2Value);
- if (SrcReg2 == 0) return false;
+ if (!SrcReg2)
+ return false;
}
// We have i1, i8, or i16, we need to either zero extend or sign extend.
if (needsExt) {
SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
- if (SrcReg1 == 0) return false;
+ if (!SrcReg1)
+ return false;
if (!UseImm) {
SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
- if (SrcReg2 == 0) return false;
+ if (!SrcReg2)
+ return false;
}
}
@@ -1474,7 +1484,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
: &ARM::GPRRegClass;
Register DestReg = createResultReg(RC);
Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
- unsigned ZeroReg = fastMaterializeConstant(Zero);
+ Register ZeroReg = fastMaterializeConstant(Zero);
// ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(MovCCOpc), DestReg)
.addReg(ZeroReg).addImm(1)
@@ -1493,7 +1503,8 @@ bool ARMFastISel::SelectFPExt(const Instruction *I) {
!V->getType()->isFloatTy()) return false;
Register Op = getRegForValue(V);
- if (Op == 0) return false;
+ if (!Op)
+ return false;
Register Result = createResultReg(&ARM::DPRRegClass);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
@@ -1512,7 +1523,8 @@ bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
V->getType()->isDoubleTy())) return false;
Register Op = getRegForValue(V);
- if (Op == 0) return false;
+ if (!Op)
+ return false;
Register Result = createResultReg(&ARM::SPRRegClass);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
@@ -1540,19 +1552,22 @@ bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
return false;
Register SrcReg = getRegForValue(Src);
- if (SrcReg == 0) return false;
+ if (!SrcReg)
+ return false;
// Handle sign-extension.
if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
/*isZExt*/!isSigned);
- if (SrcReg == 0) return false;
+ if (!SrcReg)
+ return false;
}
// The conversion routine works on fp-reg to fp-reg and the operand above
// was an integer, move it to the fp registers if possible.
- unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
- if (FP == 0) return false;
+ Register FP = ARMMoveToFPReg(MVT::f32, SrcReg);
+ if (!FP)
+ return false;
unsigned Opc;
if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
@@ -1577,7 +1592,8 @@ bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
return false;
Register Op = getRegForValue(I->getOperand(0));
- if (Op == 0) return false;
+ if (!Op)
+ return false;
unsigned Opc;
Type *OpTy = I->getOperand(0)->getType();
@@ -1593,8 +1609,9 @@ bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
// This result needs to be in an integer register, but the conversion only
// takes place in fp-regs.
- unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
- if (IntReg == 0) return false;
+ Register IntReg = ARMMoveToIntReg(DstVT, ResultReg);
+ if (!IntReg)
+ return false;
updateValueMap(I, IntReg);
return true;
@@ -1609,9 +1626,11 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
if (VT != MVT::i32) return false;
Register CondReg = getRegForValue(I->getOperand(0));
- if (CondReg == 0) return false;
+ if (!CondReg)
+ return false;
Register Op1Reg = getRegForValue(I->getOperand(1));
- if (Op1Reg == 0) return false;
+ if (!Op1Reg)
+ return false;
// Check to see if we can use an immediate in the conditional move.
int Imm = 0;
@@ -1628,10 +1647,11 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
(ARM_AM::getSOImmVal(Imm) != -1);
}
- unsigned Op2Reg = 0;
+ Register Op2Reg;
if (!UseImm) {
Op2Reg = getRegForValue(I->getOperand(2));
- if (Op2Reg == 0) return false;
+ if (!Op2Reg)
+ return false;
}
unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
@@ -1757,12 +1777,14 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
}
Register SrcReg1 = getRegForValue(I->getOperand(0));
- if (SrcReg1 == 0) return false;
+ if (!SrcReg1)
+ return false;
// TODO: Often the 2nd operand is an immediate, which can be encoded directly
// in the instruction, rather then materializing the value in a register.
Register SrcReg2 = getRegForValue(I->getOperand(1));
- if (SrcReg2 == 0) return false;
+ if (!SrcReg2)
+ return false;
Register ResultReg = createResultReg(&ARM::GPRnopcRegClass);
SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
@@ -1808,10 +1830,12 @@ bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
break;
}
Register Op1 = getRegForValue(I->getOperand(0));
- if (Op1 == 0) return false;
+ if (!Op1)
+ return false;
Register Op2 = getRegForValue(I->getOperand(1));
- if (Op2 == 0) return false;
+ if (!Op2)
+ return false;
Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
@@ -1953,7 +1977,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
case CCValAssign::SExt: {
MVT DestVT = VA.getLocVT();
Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
- assert(Arg != 0 && "Failed to emit a sext");
+ assert(Arg && "Failed to emit a sext");
ArgVT = DestVT;
break;
}
@@ -1962,13 +1986,13 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
case CCValAssign::ZExt: {
MVT DestVT = VA.getLocVT();
Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
- assert(Arg != 0 && "Failed to emit a zext");
+ assert(Arg && "Failed to emit a zext");
ArgVT = DestVT;
break;
}
case CCValAssign::BCvt: {
- unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg);
- assert(BC != 0 && "Failed to emit a bitcast!");
+ Register BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg);
+ assert(BC && "Failed to emit a bitcast!");
Arg = BC;
ArgVT = VA.getLocVT();
break;
@@ -2091,7 +2115,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
return false;
// Build a list of return value registers.
- SmallVector<unsigned, 4> RetRegs;
+ SmallVector<Register, 4> RetRegs;
CallingConv::ID CC = F.getCallingConv();
if (Ret->getNumOperands() > 0) {
@@ -2106,7 +2130,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
const Value *RV = Ret->getOperand(0);
Register Reg = getRegForValue(RV);
- if (Reg == 0)
+ if (!Reg)
return false;
// Only handle a single return value for now.
@@ -2122,7 +2146,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
if (!VA.isRegLoc())
return false;
- unsigned SrcReg = Reg + VA.getValNo();
+ Register SrcReg = Reg + VA.getValNo();
EVT RVEVT = TLI.getValueType(DL, RV->getType());
if (!RVEVT.isSimple()) return false;
MVT RVVT = RVEVT.getSimpleVT();
@@ -2138,7 +2162,8 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
// nothing.
if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
- if (SrcReg == 0) return false;
+ if (!SrcReg)
+ return false;
}
}
@@ -2167,7 +2192,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(RetOpc));
AddOptionalDefs(MIB);
- for (unsigned R : RetRegs)
+ for (Register R : RetRegs)
MIB.addReg(R, RegState::Implicit);
return true;
}
@@ -2179,11 +2204,12 @@ unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
return isThumb2 ? ARM::tBL : ARM::BL;
}
-unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
+Register ARMFastISel::getLibcallReg(const Twine &Name) {
// Manually compute the global's type to avoid building it when unnecessary.
Type *GVTy = PointerType::get(*Context, /*AS=*/0);
EVT LCREVT = TLI.getValueType(DL, GVTy);
- if (!LCREVT.isSimple()) return 0;
+ if (!LCREVT.isSimple())
+ return Register();
GlobalValue *GV = M.getNamedGlobal(Name.str());
if (!GV)
@@ -2231,7 +2257,8 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
ArgFlags.reserve(I->getNumOperands());
for (Value *Op : I->operands()) {
Register Arg = getRegForValue(Op);
- if (Arg == 0) return false;
+ if (!Arg)
+ return false;
Type *ArgTy = Op->getType();
MVT ArgVT;
@@ -2256,7 +2283,8 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
Register CalleeReg;
if (Subtarget->genLongCalls()) {
CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
- if (CalleeReg == 0) return false;
+ if (!CalleeReg)
+ return false;
}
// Issue the call.
@@ -2397,7 +2425,8 @@ bool ARMFastISel::SelectCall(const Instruction *I,
else
CalleeReg = getRegForValue(Callee);
- if (CalleeReg == 0) return false;
+ if (!CalleeReg)
+ return false;
}
// Issue the call.
@@ -2499,14 +2528,14 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
const ARMBaseRegisterInfo *RegInfo =
static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
Register FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
- unsigned SrcReg = FramePtr;
+ Register SrcReg = FramePtr;
// Recursively load frame address
// ldr r0 [fp]
// ldr r0 [r0]
// ldr r0 [r0]
// ...
- unsigned DestReg;
+ Register DestReg;
unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
while (Depth--) {
DestReg = createResultReg(RC);
@@ -2604,12 +2633,12 @@ bool ARMFastISel::SelectTrunc(const Instruction *I) {
return true;
}
-unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+Register ARMFastISel::ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
bool isZExt) {
if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
- return 0;
+ return Register();
if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
- return 0;
+ return Register();
// Table of which combinations can be emitted as a single instruction,
// and which will require two.
@@ -2704,7 +2733,7 @@ unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
// 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
bool setsCPSR = &ARM::tGPRRegClass == RC;
unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
- unsigned ResultReg;
+ Register ResultReg;
// MOVsi encodes shift and immediate in shift operand addressing mode.
// The following condition has the same value when emitting two
// instruction sequences: both are shifts.
@@ -2762,8 +2791,9 @@ bool ARMFastISel::SelectIntExt(const Instruction *I) {
MVT SrcVT = SrcEVT.getSimpleVT();
MVT DestVT = DestEVT.getSimpleVT();
- unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
- if (ResultReg == 0) return false;
+ Register ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
+ if (!ResultReg)
+ return false;
updateValueMap(I, ResultReg);
return true;
}
@@ -2796,16 +2826,19 @@ bool ARMFastISel::SelectShift(const Instruction *I,
Value *Src1Value = I->getOperand(0);
Register Reg1 = getRegForValue(Src1Value);
- if (Reg1 == 0) return false;
+ if (!Reg1)
+ return false;
- unsigned Reg2 = 0;
+ Register Reg2;
if (Opc == ARM::MOVsr) {
Reg2 = getRegForValue(Src2Value);
- if (Reg2 == 0) return false;
+ if (!Reg2)
+ return false;
}
Register ResultReg = createResultReg(&ARM::GPRnopcRegClass);
- if(ResultReg == 0) return false;
+ if (!ResultReg)
+ return false;
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(Opc), ResultReg)
@@ -2953,7 +2986,7 @@ bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
return true;
}
-unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, MVT VT) {
+Register ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, MVT VT) {
bool UseGOT_PREL = !GV->isDSOLocal();
LLVMContext *Context = &MF->getFunction().getContext();
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
@@ -3062,7 +3095,7 @@ bool ARMFastISel::fastLowerArguments() {
const TargetRegisterClass *RC = &ARM::rGPRRegClass;
for (const Argument &Arg : F->args()) {
unsigned ArgNo = Arg.getArgNo();
- unsigned SrcReg = GPRArgRegs[ArgNo];
+ MCRegister SrcReg = GPRArgRegs[ArgNo];
Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
// FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
// Without this, EmitLiveInCopies may eliminate the livein if its only
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