[llvm] 1649ca5 - [AArch64] Use Register in AArch64FastISel.cpp. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 8 17:25:40 PST 2025
Author: Craig Topper
Date: 2025-03-08T17:24:51-08:00
New Revision: 1649ca5af07a40948ea409ca055330bec1419e72
URL: https://github.com/llvm/llvm-project/commit/1649ca5af07a40948ea409ca055330bec1419e72
DIFF: https://github.com/llvm/llvm-project/commit/1649ca5af07a40948ea409ca055330bec1419e72.diff
LOG: [AArch64] Use Register in AArch64FastISel.cpp. NFC
Added:
Modified:
llvm/lib/Target/AArch64/AArch64FastISel.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index 3ddc694cc8384..8961283fe7449 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -93,7 +93,7 @@ class AArch64FastISel final : public FastISel {
unsigned Reg;
int FI;
} Base;
- unsigned OffsetReg = 0;
+ Register OffsetReg;
unsigned Shift = 0;
int64_t Offset = 0;
const GlobalValue *GV = nullptr;
@@ -108,23 +108,19 @@ class AArch64FastISel final : public FastISel {
bool isRegBase() const { return Kind == RegBase; }
bool isFIBase() const { return Kind == FrameIndexBase; }
- void setReg(unsigned Reg) {
+ void setReg(Register Reg) {
assert(isRegBase() && "Invalid base register access!");
- Base.Reg = Reg;
+ Base.Reg = Reg.id();
}
- unsigned getReg() const {
+ Register getReg() const {
assert(isRegBase() && "Invalid base register access!");
return Base.Reg;
}
- void setOffsetReg(unsigned Reg) {
- OffsetReg = Reg;
- }
+ void setOffsetReg(Register Reg) { OffsetReg = Reg; }
- unsigned getOffsetReg() const {
- return OffsetReg;
- }
+ Register getOffsetReg() const { return OffsetReg; }
void setFI(unsigned FI) {
assert(isFIBase() && "Invalid base frame index access!");
@@ -197,24 +193,23 @@ class AArch64FastISel final : public FastISel {
const Value *Cond);
bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
bool optimizeSelect(const SelectInst *SI);
- unsigned getRegForGEPIndex(const Value *Idx);
+ Register getRegForGEPIndex(const Value *Idx);
// Emit helper routines.
- unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
+ Register emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
const Value *RHS, bool SetFlags = false,
- bool WantResult = true, bool IsZExt = false);
- unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg, bool SetFlags = false,
+ bool WantResult = true, bool IsZExt = false);
+ Register emitAddSub_rr(bool UseAdd, MVT RetVT, Register LHSReg,
+ Register RHSReg, bool SetFlags = false,
bool WantResult = true);
- unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
- uint64_t Imm, bool SetFlags = false,
- bool WantResult = true);
- unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
+ Register emitAddSub_ri(bool UseAdd, MVT RetVT, Register LHSReg, uint64_t Imm,
+ bool SetFlags = false, bool WantResult = true);
+ Register emitAddSub_rs(bool UseAdd, MVT RetVT, Register LHSReg,
+ Register RHSReg, AArch64_AM::ShiftExtendType ShiftType,
uint64_t ShiftImm, bool SetFlags = false,
bool WantResult = true);
- unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
+ Register emitAddSub_rx(bool UseAdd, MVT RetVT, Register LHSReg,
+ Register RHSReg, AArch64_AM::ShiftExtendType ExtType,
uint64_t ShiftImm, bool SetFlags = false,
bool WantResult = true);
@@ -222,51 +217,51 @@ class AArch64FastISel final : public FastISel {
bool emitCompareAndBranch(const BranchInst *BI);
bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
- bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
+ bool emitICmp_ri(MVT RetVT, Register LHSReg, uint64_t Imm);
bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
- unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
+ Register emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
MachineMemOperand *MMO = nullptr);
- bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
+ bool emitStore(MVT VT, Register SrcReg, Address Addr,
MachineMemOperand *MMO = nullptr);
- bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
+ bool emitStoreRelease(MVT VT, Register SrcReg, Register AddrReg,
MachineMemOperand *MMO = nullptr);
- unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
- unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
- unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
+ Register emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
+ Register emiti1Ext(Register SrcReg, MVT DestVT, bool isZExt);
+ Register emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags = false, bool WantResult = true,
bool IsZExt = false);
- unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
- unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
+ Register emitAdd_ri_(MVT VT, Register Op0, int64_t Imm);
+ Register emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags = false, bool WantResult = true,
bool IsZExt = false);
- unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
+ Register emitSubs_rr(MVT RetVT, Register LHSReg, Register RHSReg,
bool WantResult = true);
- unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
+ Register emitSubs_rs(MVT RetVT, Register LHSReg, Register RHSReg,
AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
bool WantResult = true);
- unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
+ Register emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
const Value *RHS);
- unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
+ Register emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, Register LHSReg,
uint64_t Imm);
- unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg, uint64_t ShiftImm);
- unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
- unsigned emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1);
- unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
- unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
- unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
- unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
+ Register emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, Register LHSReg,
+ Register RHSReg, uint64_t ShiftImm);
+ Register emitAnd_ri(MVT RetVT, Register LHSReg, uint64_t Imm);
+ Register emitMul_rr(MVT RetVT, Register Op0, Register Op1);
+ Register emitSMULL_rr(MVT RetVT, Register Op0, Register Op1);
+ Register emitUMULL_rr(MVT RetVT, Register Op0, Register Op1);
+ Register emitLSL_rr(MVT RetVT, Register Op0Reg, Register Op1Reg);
+ Register emitLSL_ri(MVT RetVT, MVT SrcVT, Register Op0Reg, uint64_t Imm,
bool IsZExt = true);
- unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
- unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
+ Register emitLSR_rr(MVT RetVT, Register Op0Reg, Register Op1Reg);
+ Register emitLSR_ri(MVT RetVT, MVT SrcVT, Register Op0Reg, uint64_t Imm,
bool IsZExt = true);
- unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
- unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
+ Register emitASR_rr(MVT RetVT, Register Op0Reg, Register Op1Reg);
+ Register emitASR_ri(MVT RetVT, MVT SrcVT, Register Op0Reg, uint64_t Imm,
bool IsZExt = false);
- unsigned materializeInt(const ConstantInt *CI, MVT VT);
- unsigned materializeFP(const ConstantFP *CFP, MVT VT);
- unsigned materializeGV(const GlobalValue *GV);
+ Register materializeInt(const ConstantInt *CI, MVT VT);
+ Register materializeFP(const ConstantFP *CFP, MVT VT);
+ Register materializeGV(const GlobalValue *GV);
// Call handling routines.
private:
@@ -370,9 +365,9 @@ Register AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
return Register();
}
-unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
+Register AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
if (VT > MVT::i64)
- return 0;
+ return Register();
if (!CI->isZero())
return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
@@ -387,14 +382,14 @@ unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
return ResultReg;
}
-unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
+Register AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
// Positive zero (+0.0) has to be materialized with a fmov from the zero
// register, because the immediate version of fmov cannot encode zero.
if (CFP->isNullValue())
return fastMaterializeFloatZero(CFP);
if (VT != MVT::f32 && VT != MVT::f64)
- return 0;
+ return Register();
const APFloat Val = CFP->getValueAPF();
bool Is64Bit = (VT == MVT::f64);
@@ -442,27 +437,27 @@ unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
return ResultReg;
}
-unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
+Register AArch64FastISel::materializeGV(const GlobalValue *GV) {
// We can't handle thread-local variables quickly yet.
if (GV->isThreadLocal())
- return 0;
+ return Register();
// MachO still uses GOT for large code-model accesses, but ELF requires
// movz/movk sequences, which FastISel doesn't handle yet.
if (!Subtarget->useSmallAddressing() && !Subtarget->isTargetMachO())
- return 0;
+ return Register();
if (FuncInfo.MF->getInfo<AArch64FunctionInfo>()->hasELFSignedGOT())
- return 0;
+ return Register();
unsigned OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
EVT DestEVT = TLI.getValueType(DL, GV->getType(), true);
if (!DestEVT.isSimple())
- return 0;
+ return Register();
Register ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
- unsigned ResultReg;
+ Register ResultReg;
if (OpFlags & AArch64II::MO_GOT) {
// ADRP + LDRX
@@ -516,7 +511,7 @@ unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
// are not exactly 1:1 with FastISel so we cannot easily abstract this
// out. At some point, it would be nice to find a way to not have this
// duplciate code.
- unsigned DstReg = createResultReg(&AArch64::GPR64commonRegClass);
+ Register DstReg = createResultReg(&AArch64::GPR64commonRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::MOVKXi),
DstReg)
.addReg(ADRPReg)
@@ -979,7 +974,7 @@ bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
// If all else fails, try to materialize the value in a register.
if (!Addr.getGlobalValue()) {
Addr.setReg(getRegForValue(V));
- return Addr.getReg() != 0;
+ return Addr.getReg().isValid();
}
return false;
@@ -1075,7 +1070,7 @@ bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
}
if (RegisterOffsetNeedsLowering) {
- unsigned ResultReg = 0;
+ Register ResultReg;
if (Addr.getReg()) {
if (Addr.getExtendType() == AArch64_AM::SXTW ||
Addr.getExtendType() == AArch64_AM::UXTW )
@@ -1109,7 +1104,7 @@ bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
// Since the offset is too large for the load/store instruction get the
// reg+offset into a register.
if (ImmediateOffsetNeedsLowering) {
- unsigned ResultReg;
+ Register ResultReg;
if (Addr.getReg())
// Try to fold the immediate into the add instruction.
ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), Offset);
@@ -1164,14 +1159,14 @@ void AArch64FastISel::addLoadStoreOperands(Address &Addr,
MIB.addMemOperand(MMO);
}
-unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
+Register AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
const Value *RHS, bool SetFlags,
- bool WantResult, bool IsZExt) {
+ bool WantResult, bool IsZExt) {
AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
bool NeedExtend = false;
switch (RetVT.SimpleTy) {
default:
- return 0;
+ return Register();
case MVT::i1:
NeedExtend = true;
break;
@@ -1210,12 +1205,12 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
Register LHSReg = getRegForValue(LHS);
if (!LHSReg)
- return 0;
+ return Register();
if (NeedExtend)
LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
- unsigned ResultReg = 0;
+ Register ResultReg;
if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
if (C->isNegative())
@@ -1236,7 +1231,7 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
isValueAvailable(RHS)) {
Register RHSReg = getRegForValue(RHS);
if (!RHSReg)
- return 0;
+ return Register();
return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
SetFlags, WantResult);
}
@@ -1255,7 +1250,7 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
Register RHSReg = getRegForValue(MulLHS);
if (!RHSReg)
- return 0;
+ return Register();
ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
ShiftVal, SetFlags, WantResult);
if (ResultReg)
@@ -1278,7 +1273,7 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
if (ShiftType != AArch64_AM::InvalidShiftExtend) {
Register RHSReg = getRegForValue(SI->getOperand(0));
if (!RHSReg)
- return 0;
+ return Register();
ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
ShiftVal, SetFlags, WantResult);
if (ResultReg)
@@ -1290,7 +1285,7 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
Register RHSReg = getRegForValue(RHS);
if (!RHSReg)
- return 0;
+ return Register();
if (NeedExtend)
RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
@@ -1298,17 +1293,17 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
}
-unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg, bool SetFlags,
+Register AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, Register LHSReg,
+ Register RHSReg, bool SetFlags,
bool WantResult) {
assert(LHSReg && RHSReg && "Invalid register number.");
if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||
RHSReg == AArch64::SP || RHSReg == AArch64::WSP)
- return 0;
+ return Register();
if (RetVT != MVT::i32 && RetVT != MVT::i64)
- return 0;
+ return Register();
static const unsigned OpcTable[2][2][2] = {
{ { AArch64::SUBWrr, AArch64::SUBXrr },
@@ -1320,7 +1315,7 @@ unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
const TargetRegisterClass *RC =
Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
- unsigned ResultReg;
+ Register ResultReg;
if (WantResult)
ResultReg = createResultReg(RC);
else
@@ -1335,13 +1330,13 @@ unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
return ResultReg;
}
-unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
+Register AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, Register LHSReg,
uint64_t Imm, bool SetFlags,
bool WantResult) {
assert(LHSReg && "Invalid register number.");
if (RetVT != MVT::i32 && RetVT != MVT::i64)
- return 0;
+ return Register();
unsigned ShiftImm;
if (isUInt<12>(Imm))
@@ -1350,7 +1345,7 @@ unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
ShiftImm = 12;
Imm >>= 12;
} else
- return 0;
+ return Register();
static const unsigned OpcTable[2][2][2] = {
{ { AArch64::SUBWri, AArch64::SUBXri },
@@ -1365,7 +1360,7 @@ unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
else
RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
- unsigned ResultReg;
+ Register ResultReg;
if (WantResult)
ResultReg = createResultReg(RC);
else
@@ -1380,8 +1375,8 @@ unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
return ResultReg;
}
-unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg,
+Register AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, Register LHSReg,
+ Register RHSReg,
AArch64_AM::ShiftExtendType ShiftType,
uint64_t ShiftImm, bool SetFlags,
bool WantResult) {
@@ -1390,11 +1385,11 @@ unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
RHSReg != AArch64::SP && RHSReg != AArch64::WSP);
if (RetVT != MVT::i32 && RetVT != MVT::i64)
- return 0;
+ return Register();
// Don't deal with undefined shifts.
if (ShiftImm >= RetVT.getSizeInBits())
- return 0;
+ return Register();
static const unsigned OpcTable[2][2][2] = {
{ { AArch64::SUBWrs, AArch64::SUBXrs },
@@ -1406,7 +1401,7 @@ unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
const TargetRegisterClass *RC =
Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
- unsigned ResultReg;
+ Register ResultReg;
if (WantResult)
ResultReg = createResultReg(RC);
else
@@ -1422,8 +1417,8 @@ unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
return ResultReg;
}
-unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
- unsigned RHSReg,
+Register AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, Register LHSReg,
+ Register RHSReg,
AArch64_AM::ShiftExtendType ExtType,
uint64_t ShiftImm, bool SetFlags,
bool WantResult) {
@@ -1432,10 +1427,10 @@ unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
RHSReg != AArch64::XZR && RHSReg != AArch64::WZR);
if (RetVT != MVT::i32 && RetVT != MVT::i64)
- return 0;
+ return Register();
if (ShiftImm >= 4)
- return 0;
+ return Register();
static const unsigned OpcTable[2][2][2] = {
{ { AArch64::SUBWrx, AArch64::SUBXrx },
@@ -1450,7 +1445,7 @@ unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
else
RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
- unsigned ResultReg;
+ Register ResultReg;
if (WantResult)
ResultReg = createResultReg(RC);
else
@@ -1491,12 +1486,14 @@ bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
bool IsZExt) {
return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
- IsZExt) != 0;
+ IsZExt)
+ .isValid();
}
-bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) {
+bool AArch64FastISel::emitICmp_ri(MVT RetVT, Register LHSReg, uint64_t Imm) {
return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,
- /*SetFlags=*/true, /*WantResult=*/false) != 0;
+ /*SetFlags=*/true, /*WantResult=*/false)
+ .isValid();
}
bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
@@ -1532,7 +1529,7 @@ bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
return true;
}
-unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
+Register AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags, bool WantResult, bool IsZExt) {
return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
IsZExt);
@@ -1543,8 +1540,8 @@ unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
/// First try to emit an add with an immediate operand using emitAddSub_ri. If
/// that fails, then try to materialize the immediate into a register and use
/// emitAddSub_rr instead.
-unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm) {
- unsigned ResultReg;
+Register AArch64FastISel::emitAdd_ri_(MVT VT, Register Op0, int64_t Imm) {
+ Register ResultReg;
if (Imm < 0)
ResultReg = emitAddSub_ri(false, VT, Op0, -Imm);
else
@@ -1553,35 +1550,35 @@ unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm) {
if (ResultReg)
return ResultReg;
- unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm);
+ Register CReg = fastEmit_i(VT, VT, ISD::Constant, Imm);
if (!CReg)
- return 0;
+ return Register();
ResultReg = emitAddSub_rr(true, VT, Op0, CReg);
return ResultReg;
}
-unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
+Register AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags, bool WantResult, bool IsZExt) {
return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
IsZExt);
}
-unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
- unsigned RHSReg, bool WantResult) {
+Register AArch64FastISel::emitSubs_rr(MVT RetVT, Register LHSReg,
+ Register RHSReg, bool WantResult) {
return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
/*SetFlags=*/true, WantResult);
}
-unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
- unsigned RHSReg,
+Register AArch64FastISel::emitSubs_rs(MVT RetVT, Register LHSReg,
+ Register RHSReg,
AArch64_AM::ShiftExtendType ShiftType,
uint64_t ShiftImm, bool WantResult) {
return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
ShiftImm, /*SetFlags=*/true, WantResult);
}
-unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
+Register AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
const Value *LHS, const Value *RHS) {
// Canonicalize immediates to the RHS first.
if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
@@ -1600,9 +1597,9 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
Register LHSReg = getRegForValue(LHS);
if (!LHSReg)
- return 0;
+ return Register();
- unsigned ResultReg = 0;
+ Register ResultReg;
if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
uint64_t Imm = C->getZExtValue();
ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
@@ -1625,7 +1622,7 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
Register RHSReg = getRegForValue(MulLHS);
if (!RHSReg)
- return 0;
+ return Register();
ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
if (ResultReg)
return ResultReg;
@@ -1639,7 +1636,7 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
uint64_t ShiftVal = C->getZExtValue();
Register RHSReg = getRegForValue(SI->getOperand(0));
if (!RHSReg)
- return 0;
+ return Register();
ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
if (ResultReg)
return ResultReg;
@@ -1648,7 +1645,7 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
Register RHSReg = getRegForValue(RHS);
if (!RHSReg)
- return 0;
+ return Register();
MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
@@ -1659,8 +1656,8 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
return ResultReg;
}
-unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
- unsigned LHSReg, uint64_t Imm) {
+Register AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
+ Register LHSReg, uint64_t Imm) {
static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
"ISD nodes are not consecutive!");
static const unsigned OpcTable[3][2] = {
@@ -1673,7 +1670,7 @@ unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
unsigned RegSize;
switch (RetVT.SimpleTy) {
default:
- return 0;
+ return Register();
case MVT::i1:
case MVT::i8:
case MVT::i16:
@@ -1692,7 +1689,7 @@ unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
}
if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
- return 0;
+ return Register();
Register ResultReg =
fastEmitInst_ri(Opc, RC, LHSReg,
@@ -1704,8 +1701,8 @@ unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
return ResultReg;
}
-unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
- unsigned LHSReg, unsigned RHSReg,
+Register AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
+ Register LHSReg, Register RHSReg,
uint64_t ShiftImm) {
static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
"ISD nodes are not consecutive!");
@@ -1717,13 +1714,13 @@ unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
// Don't deal with undefined shifts.
if (ShiftImm >= RetVT.getSizeInBits())
- return 0;
+ return Register();
const TargetRegisterClass *RC;
unsigned Opc;
switch (RetVT.SimpleTy) {
default:
- return 0;
+ return Register();
case MVT::i1:
case MVT::i8:
case MVT::i16:
@@ -1746,19 +1743,18 @@ unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
return ResultReg;
}
-unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg,
- uint64_t Imm) {
+Register AArch64FastISel::emitAnd_ri(MVT RetVT, Register LHSReg, uint64_t Imm) {
return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm);
}
-unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
+Register AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
bool WantZExt, MachineMemOperand *MMO) {
if (!TLI.allowsMisalignedMemoryAccesses(VT))
- return 0;
+ return Register();
// Simplify this down to something we can handle.
if (!simplifyAddress(Addr, VT))
- return 0;
+ return Register();
unsigned ScaleFactor = getImplicitScaleFactor(VT);
if (!ScaleFactor)
@@ -1869,7 +1865,7 @@ unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
// Loading an i1 requires special handling.
if (VT == MVT::i1) {
- unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1);
+ Register ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1);
assert(ANDReg && "Unexpected AND instruction emission failure.");
ResultReg = ANDReg;
}
@@ -1896,7 +1892,7 @@ bool AArch64FastISel::selectAddSub(const Instruction *I) {
if (VT.isVector())
return selectOperator(I, I->getOpcode());
- unsigned ResultReg;
+ Register ResultReg;
switch (I->getOpcode()) {
default:
llvm_unreachable("Unexpected instruction.");
@@ -1922,7 +1918,7 @@ bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
if (VT.isVector())
return selectOperator(I, I->getOpcode());
- unsigned ResultReg;
+ Register ResultReg;
switch (I->getOpcode()) {
default:
llvm_unreachable("Unexpected instruction.");
@@ -1991,7 +1987,7 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
}
}
- unsigned ResultReg =
+ Register ResultReg =
emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
if (!ResultReg)
return false;
@@ -2054,8 +2050,8 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
return true;
}
-bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg,
- unsigned AddrReg,
+bool AArch64FastISel::emitStoreRelease(MVT VT, Register SrcReg,
+ Register AddrReg,
MachineMemOperand *MMO) {
unsigned Opc;
switch (VT.SimpleTy) {
@@ -2076,7 +2072,7 @@ bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg,
return true;
}
-bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
+bool AArch64FastISel::emitStore(MVT VT, Register SrcReg, Address Addr,
MachineMemOperand *MMO) {
if (!TLI.allowsMisalignedMemoryAccesses(VT))
return false;
@@ -2130,7 +2126,7 @@ bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
// Storing an i1 requires special handling.
if (VTIsi1 && SrcReg != AArch64::WZR) {
- unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, 1);
+ Register ANDReg = emitAnd_ri(MVT::i32, SrcReg, 1);
assert(ANDReg && "Unexpected AND instruction emission failure.");
SrcReg = ANDReg;
}
@@ -2170,7 +2166,7 @@ bool AArch64FastISel::selectStore(const Instruction *I) {
// Get the value to be stored into a register. Use the zero register directly
// when possible to avoid an unnecessary copy and a wasted register.
- unsigned SrcReg = 0;
+ Register SrcReg;
if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
if (CI->isZero())
SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
@@ -2490,7 +2486,7 @@ bool AArch64FastISel::selectBranch(const Instruction *I) {
}
Register CondReg = getRegForValue(BI->getCondition());
- if (CondReg == 0)
+ if (!CondReg)
return false;
// i1 conditions come as i32 values, test the lowest bit with tb(n)z.
@@ -2515,7 +2511,7 @@ bool AArch64FastISel::selectBranch(const Instruction *I) {
bool AArch64FastISel::selectIndirectBr(const Instruction *I) {
const IndirectBrInst *BI = cast<IndirectBrInst>(I);
Register AddrReg = getRegForValue(BI->getOperand(0));
- if (AddrReg == 0)
+ if (!AddrReg)
return false;
// Authenticated indirectbr is not implemented yet.
@@ -2543,7 +2539,7 @@ bool AArch64FastISel::selectCmp(const Instruction *I) {
// Try to optimize or fold the cmp.
CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
- unsigned ResultReg = 0;
+ Register ResultReg;
switch (Predicate) {
default:
break;
@@ -2831,7 +2827,7 @@ bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {
return false;
Register SrcReg = getRegForValue(I->getOperand(0));
- if (SrcReg == 0)
+ if (!SrcReg)
return false;
EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
@@ -3120,7 +3116,7 @@ bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, unsigned NumBytes) {
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
MVT CopyVT = VA.getValVT();
- unsigned CopyReg = ResultReg + i;
+ Register CopyReg = ResultReg + i;
// TODO: Handle big-endian results
if (CopyVT.isVector() && !Subtarget->isLittleEndian())
@@ -3249,7 +3245,7 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
} else
return false;
} else {
- unsigned CallReg = 0;
+ Register CallReg;
if (Symbol) {
Register ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::ADRP),
@@ -3330,7 +3326,7 @@ bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
}
}
- unsigned ResultReg = emitLoad(VT, VT, Src);
+ Register ResultReg = emitLoad(VT, VT, Src);
if (!ResultReg)
return false;
@@ -3457,7 +3453,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
// ldr x0, [x0]
// ldr x0, [x0]
// ...
- unsigned DestReg;
+ Register DestReg;
unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
while (Depth--) {
DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
@@ -3639,7 +3635,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
if (!Op0Reg)
return false;
- unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);
+ Register ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);
if (!ResultReg)
return false;
@@ -3691,7 +3687,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
break;
}
- unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
+ Register ResultReg1, ResultReg2, MulReg;
AArch64CC::CondCode CC = AArch64CC::Invalid;
switch (IID) {
default: llvm_unreachable("Unexpected intrinsic!");
@@ -3735,7 +3731,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
// LHSReg and RHSReg cannot be killed by this Mul, since they are
// reused in the next instruction.
MulReg = emitMul_rr(VT, LHSReg, RHSReg);
- unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);
+ Register SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);
emitSubs_rs(VT, SMULHReg, MulReg, AArch64_AM::ASR, 63,
/*WantResult=*/false);
}
@@ -3764,7 +3760,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
// LHSReg and RHSReg cannot be killed by this Mul, since they are
// reused in the next instruction.
MulReg = emitMul_rr(VT, LHSReg, RHSReg);
- unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
+ Register UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
emitSubs_rr(VT, AArch64::XZR, UMULHReg, /*WantResult=*/false);
}
break;
@@ -3862,7 +3858,7 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
return false;
// Build a list of return value registers.
- SmallVector<unsigned, 4> RetRegs;
+ SmallVector<Register, 4> RetRegs;
if (Ret->getNumOperands() > 0) {
CallingConv::ID CC = F.getCallingConv();
@@ -3891,10 +3887,10 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
return false;
Register Reg = getRegForValue(RV);
- if (Reg == 0)
+ if (!Reg)
return false;
- unsigned SrcReg = Reg + VA.getValNo();
+ Register SrcReg = Reg + VA.getValNo();
Register DestReg = VA.getLocReg();
// Avoid a cross-class copy. This is very unlikely.
if (!MRI.getRegClass(SrcReg)->contains(DestReg))
@@ -3924,7 +3920,7 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
bool IsZExt = Outs[0].Flags.isZExt();
SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
- if (SrcReg == 0)
+ if (!SrcReg)
return false;
}
@@ -3943,7 +3939,7 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::RET_ReallyLR));
- for (unsigned RetReg : RetRegs)
+ for (Register RetReg : RetRegs)
MIB.addReg(RetReg, RegState::Implicit);
return true;
}
@@ -3979,7 +3975,7 @@ bool AArch64FastISel::selectTrunc(const Instruction *I) {
// generate a COPY. We cannot mark the source register also as result
// register, because this can incorrectly transfer the kill flag onto the
// source register.
- unsigned ResultReg;
+ Register ResultReg;
if (SrcVT == MVT::i64) {
uint64_t Mask = 0;
switch (DestVT.SimpleTy) {
@@ -4013,7 +4009,7 @@ bool AArch64FastISel::selectTrunc(const Instruction *I) {
return true;
}
-unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
+Register AArch64FastISel::emiti1Ext(Register SrcReg, MVT DestVT, bool IsZExt) {
assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
DestVT == MVT::i64) &&
"Unexpected value type.");
@@ -4022,7 +4018,7 @@ unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
DestVT = MVT::i32;
if (IsZExt) {
- unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1);
+ Register ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1);
assert(ResultReg && "Unexpected AND instruction emission failure.");
if (DestVT == MVT::i64) {
// We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
@@ -4039,17 +4035,19 @@ unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
} else {
if (DestVT == MVT::i64) {
// FIXME: We're SExt i1 to i64.
- return 0;
+ return Register();
}
return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
0, 0);
}
}
-unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
- unsigned Opc, ZReg;
+Register AArch64FastISel::emitMul_rr(MVT RetVT, Register Op0, Register Op1) {
+ unsigned Opc;
+ Register ZReg;
switch (RetVT.SimpleTy) {
- default: return 0;
+ default:
+ return Register();
case MVT::i8:
case MVT::i16:
case MVT::i32:
@@ -4064,29 +4062,30 @@ unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
return fastEmitInst_rrr(Opc, RC, Op0, Op1, ZReg);
}
-unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+Register AArch64FastISel::emitSMULL_rr(MVT RetVT, Register Op0, Register Op1) {
if (RetVT != MVT::i64)
- return 0;
+ return Register();
return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
Op0, Op1, AArch64::XZR);
}
-unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+Register AArch64FastISel::emitUMULL_rr(MVT RetVT, Register Op0, Register Op1) {
if (RetVT != MVT::i64)
- return 0;
+ return Register();
return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
Op0, Op1, AArch64::XZR);
}
-unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg,
- unsigned Op1Reg) {
+Register AArch64FastISel::emitLSL_rr(MVT RetVT, Register Op0Reg,
+ Register Op1Reg) {
unsigned Opc = 0;
bool NeedTrunc = false;
uint64_t Mask = 0;
switch (RetVT.SimpleTy) {
- default: return 0;
+ default:
+ return Register();
case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
case MVT::i32: Opc = AArch64::LSLVWr; break;
@@ -4104,7 +4103,7 @@ unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg,
return ResultReg;
}
-unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
+Register AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, Register Op0,
uint64_t Shift, bool IsZExt) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
@@ -4135,7 +4134,7 @@ unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
// Don't deal with undefined shifts.
if (Shift >= DstBits)
- return 0;
+ return Register();
// For immediate shifts we can fold the zero-/sign-extension into the shift.
// {S|U}BFM Wd, Wn, #r, #s
@@ -4182,13 +4181,14 @@ unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
return fastEmitInst_rii(Opc, RC, Op0, ImmR, ImmS);
}
-unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
- unsigned Op1Reg) {
+Register AArch64FastISel::emitLSR_rr(MVT RetVT, Register Op0Reg,
+ Register Op1Reg) {
unsigned Opc = 0;
bool NeedTrunc = false;
uint64_t Mask = 0;
switch (RetVT.SimpleTy) {
- default: return 0;
+ default:
+ return Register();
case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
case MVT::i32: Opc = AArch64::LSRVWr; break;
@@ -4207,7 +4207,7 @@ unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
return ResultReg;
}
-unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
+Register AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, Register Op0,
uint64_t Shift, bool IsZExt) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
@@ -4238,7 +4238,7 @@ unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
// Don't deal with undefined shifts.
if (Shift >= DstBits)
- return 0;
+ return Register();
// For immediate shifts we can fold the zero-/sign-extension into the shift.
// {S|U}BFM Wd, Wn, #r, #s
@@ -4273,7 +4273,7 @@ unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
if (!IsZExt) {
Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
if (!Op0)
- return 0;
+ return Register();
SrcVT = RetVT;
SrcBits = SrcVT.getSizeInBits();
IsZExt = true;
@@ -4298,13 +4298,14 @@ unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
return fastEmitInst_rii(Opc, RC, Op0, ImmR, ImmS);
}
-unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg,
- unsigned Op1Reg) {
+Register AArch64FastISel::emitASR_rr(MVT RetVT, Register Op0Reg,
+ Register Op1Reg) {
unsigned Opc = 0;
bool NeedTrunc = false;
uint64_t Mask = 0;
switch (RetVT.SimpleTy) {
- default: return 0;
+ default:
+ return Register();
case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
case MVT::i32: Opc = AArch64::ASRVWr; break;
@@ -4323,7 +4324,7 @@ unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg,
return ResultReg;
}
-unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
+Register AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, Register Op0,
uint64_t Shift, bool IsZExt) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
@@ -4354,7 +4355,7 @@ unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
// Don't deal with undefined shifts.
if (Shift >= DstBits)
- return 0;
+ return Register();
// For immediate shifts we can fold the zero-/sign-extension into the shift.
// {S|U}BFM Wd, Wn, #r, #s
@@ -4403,7 +4404,7 @@ unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
return fastEmitInst_rii(Opc, RC, Op0, ImmR, ImmS);
}
-unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+Register AArch64FastISel::emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
bool IsZExt) {
assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
@@ -4415,14 +4416,14 @@ unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
(DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
(SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
- return 0;
+ return Register();
unsigned Opc;
unsigned Imm = 0;
switch (SrcVT.SimpleTy) {
default:
- return 0;
+ return Register();
case MVT::i1:
return emiti1Ext(SrcReg, DestVT, IsZExt);
case MVT::i8:
@@ -4604,7 +4605,7 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) {
}
}
- unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
+ Register ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
if (!ResultReg)
return false;
@@ -4697,8 +4698,7 @@ bool AArch64FastISel::selectMul(const Instruction *I) {
if (!Src0Reg)
return false;
- unsigned ResultReg =
- emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);
+ Register ResultReg = emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);
if (ResultReg) {
updateValueMap(I, ResultReg);
@@ -4714,7 +4714,7 @@ bool AArch64FastISel::selectMul(const Instruction *I) {
if (!Src1Reg)
return false;
- unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg);
+ Register ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg);
if (!ResultReg)
return false;
@@ -4732,7 +4732,7 @@ bool AArch64FastISel::selectShift(const Instruction *I) {
return selectOperator(I, I->getOpcode());
if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
- unsigned ResultReg = 0;
+ Register ResultReg;
uint64_t ShiftVal = C->getZExtValue();
MVT SrcVT = RetVT;
bool IsZExt = I->getOpcode() != Instruction::AShr;
@@ -4788,7 +4788,7 @@ bool AArch64FastISel::selectShift(const Instruction *I) {
if (!Op1Reg)
return false;
- unsigned ResultReg = 0;
+ Register ResultReg;
switch (I->getOpcode()) {
default: llvm_unreachable("Unexpected instruction.");
case Instruction::Shl:
@@ -4906,7 +4906,7 @@ bool AArch64FastISel::selectSDiv(const Instruction *I) {
return false;
if (cast<BinaryOperator>(I)->isExact()) {
- unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2);
+ Register ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2);
if (!ResultReg)
return false;
updateValueMap(I, ResultReg);
@@ -4914,7 +4914,7 @@ bool AArch64FastISel::selectSDiv(const Instruction *I) {
}
int64_t Pow2MinusOne = (1ULL << Lg2) - 1;
- unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne);
+ Register AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne);
if (!AddReg)
return false;
@@ -4938,8 +4938,8 @@ bool AArch64FastISel::selectSDiv(const Instruction *I) {
// Divide by Pow2 --> ashr. If we're dividing by a negative value we must also
// negate the result.
- unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
- unsigned ResultReg;
+ Register ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
+ Register ResultReg;
if (C.isNegative())
ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg,
AArch64_AM::ASR, Lg2);
@@ -4956,11 +4956,11 @@ bool AArch64FastISel::selectSDiv(const Instruction *I) {
/// This is mostly a copy of the existing FastISel getRegForGEPIndex code. We
/// have to duplicate it for AArch64, because otherwise we would fail during the
/// sign-extend emission.
-unsigned AArch64FastISel::getRegForGEPIndex(const Value *Idx) {
+Register AArch64FastISel::getRegForGEPIndex(const Value *Idx) {
Register IdxN = getRegForValue(Idx);
- if (IdxN == 0)
+ if (!IdxN)
// Unhandled operand. Halt "fast" selection and bail.
- return 0;
+ return Register();
// If the index is smaller or larger than intptr_t, truncate or extend it.
MVT PtrVT = TLI.getPointerTy(DL);
@@ -5015,12 +5015,12 @@ bool AArch64FastISel::selectGetElementPtr(const Instruction *I) {
// N = N + Idx * ElementSize;
uint64_t ElementSize = GTI.getSequentialElementStride(DL);
- unsigned IdxN = getRegForGEPIndex(Idx);
+ Register IdxN = getRegForGEPIndex(Idx);
if (!IdxN)
return false;
if (ElementSize != 1) {
- unsigned C = fastEmit_i(VT, VT, ISD::Constant, ElementSize);
+ Register C = fastEmit_i(VT, VT, ISD::Constant, ElementSize);
if (!C)
return false;
IdxN = emitMul_rr(VT, IdxN, C);
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