[llvm] 3e0c503 - [SPIRV] Avoid repeated hash lookups (NFC) (#130391)

[via llvm-commits]

Author: Kazu Hirata
Date: 2025-03-08T01:02:22-08:00
New Revision: 3e0c503e3e259ce63b08e5d780a82fe7385dfbc8

URL: https://github.com/llvm/llvm-project/commit/3e0c503e3e259ce63b08e5d780a82fe7385dfbc8
DIFF: https://github.com/llvm/llvm-project/commit/3e0c503e3e259ce63b08e5d780a82fe7385dfbc8.diff

LOG: [SPIRV] Avoid repeated hash lookups (NFC) (#130391)

Added: 
    

Modified: 
    llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index baacd58b28028..3779a4b6ccd34 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -120,8 +120,9 @@ addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR,
   }
   for (MachineInstr *MI : ToErase) {
     Register Reg = MI->getOperand(2).getReg();
-    if (RegsAlreadyAddedToDT.contains(MI))
-      Reg = RegsAlreadyAddedToDT[MI];
+    auto It = RegsAlreadyAddedToDT.find(MI);
+    if (It != RegsAlreadyAddedToDT.end())
+      Reg = It->second;
     auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg());
     if (!MRI.getRegClassOrNull(Reg) && RC)
       MRI.setRegClass(Reg, RC);
@@ -652,7 +653,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
   }
   for (MachineInstr *MI : ToErase) {
     auto It = RegsAlreadyAddedToDT.find(MI);
-    if (RegsAlreadyAddedToDT.contains(MI))
+    if (It != RegsAlreadyAddedToDT.end())
       MRI.replaceRegWith(MI->getOperand(0).getReg(), It->second);
     MI->eraseFromParent();
   }