[llvm] [LV] Add target-independent test for type-mismatch (PR #130295)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 7 09:06:46 PST 2025
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/130295
>From dcd7d004211018bae8d00a040f9ce497c23e47a2 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Fri, 7 Mar 2025 11:40:16 +0000
Subject: [PATCH 1/2] [LV] Add target-independent test for type-mismatch
The test suite of LoopVectorize suffers from a coverage hole when types
mismatch, in the target-independent case. There is already
interleave-allocsize-not-equal-typesize.ll under the AArch64 target
written for the purposes of fixing specific bugs, but nothing exercising
this in a target-independent fashion. Fix this by adapting a test from
LoopAccessAnalysis' depend_diff_types.ll, and demonstrate that
LoopVectorize only ever interleaves when types mismatch.
---
.../LoopVectorize/type-mismatch-interleave.ll | 222 ++++++++++++++++++
1 file changed, 222 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll
diff --git a/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll b/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll
new file mode 100644
index 0000000000000..0b4ffc9e3008d
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll
@@ -0,0 +1,222 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
+
+; Tests demonstrating that LV only ever interleaves when types mismatch.
+
+define void @different_types(ptr noalias %src.1, ptr noalias %src.2, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) {
+; CHECK-LABEL: define void @different_types(
+; CHECK-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP4]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i64> [[WIDE_LOAD]] to <4 x i32>
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP7]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD1]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP1]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP3]]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
+; CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP6]], i32 1
+; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP11]], align 4
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[TMP6]], i32 2
+; CHECK-NEXT: store i32 [[TMP16]], ptr [[TMP12]], align 4
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP6]], i32 3
+; CHECK-NEXT: store i32 [[TMP17]], ptr [[TMP13]], align 4
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr nusw i64, ptr [[TMP18]], i32 0
+; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr [[TMP19]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i64, ptr [[GEP_SRC_1]], align 4
+; CHECK-NEXT: [[LD_SRC_1_I32:%.*]] = trunc i64 [[LD_SRC_1]] to i32
+; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add i64 [[LD_SRC_1]], [[LD_SRC_2]]
+; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[IV]]
+; CHECK-NEXT: store i32 [[LD_SRC_1_I32]], ptr [[GEP_DST_1]], align 4
+; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[ADD]], ptr [[GEP_DST_2]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+
+ %gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv
+ %ld.src.1 = load i64, ptr %gep.src.1
+ %ld.src.1.i32 = trunc i64 %ld.src.1 to i32
+
+ %gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
+ %ld.src.2 = load i64, ptr %gep.src.2
+ %add = add i64 %ld.src.1, %ld.src.2
+
+ %gep.dst.1 = getelementptr nusw i64, ptr %dst.1, i64 %iv
+ store i32 %ld.src.1.i32, ptr %gep.dst.1
+
+ %gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
+ store i64 %add, ptr %gep.dst.2
+
+ %iv.next = add nuw nsw i64 %iv, 1
+ %cond = icmp ult i64 %iv.next, %n
+ br i1 %cond, label %loop, label %exit
+
+exit:
+ ret void
+}
+
+define void @different_types_rt_memcheck(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
+; CHECK-LABEL: define void @different_types_rt_memcheck(
+; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[SRC_25:%.*]] = ptrtoint ptr [[SRC_2]] to i64
+; CHECK-NEXT: [[SRC_13:%.*]] = ptrtoint ptr [[SRC_1]] to i64
+; CHECK-NEXT: [[DST_12:%.*]] = ptrtoint ptr [[DST_1]] to i64
+; CHECK-NEXT: [[DST_21:%.*]] = ptrtoint ptr [[DST_2]] to i64
+; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST_21]], [[DST_12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[DST_12]], [[SRC_13]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[DST_12]], [[SRC_25]]
+; CHECK-NEXT: [[DIFF_CHECK6:%.*]] = icmp ult i64 [[TMP2]], 32
+; CHECK-NEXT: [[CONFLICT_RDX7:%.*]] = or i1 [[CONFLICT_RDX]], [[DIFF_CHECK6]]
+; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[DST_21]], [[SRC_13]]
+; CHECK-NEXT: [[DIFF_CHECK8:%.*]] = icmp ult i64 [[TMP3]], 32
+; CHECK-NEXT: [[CONFLICT_RDX9:%.*]] = or i1 [[CONFLICT_RDX7]], [[DIFF_CHECK8]]
+; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[DST_21]], [[SRC_25]]
+; CHECK-NEXT: [[DIFF_CHECK10:%.*]] = icmp ult i64 [[TMP4]], 32
+; CHECK-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX9]], [[DIFF_CHECK10]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX11]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 3
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP9]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = trunc <4 x i64> [[WIDE_LOAD]] to <4 x i32>
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[TMP12]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i64>, ptr [[TMP13]], align 4
+; CHECK-NEXT: [[TMP14:%.*]] = add <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD12]]
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP6]]
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP8]]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i32> [[TMP11]], i32 0
+; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP15]], align 4
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[TMP11]], i32 1
+; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP16]], align 4
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i32> [[TMP11]], i32 2
+; CHECK-NEXT: store i32 [[TMP21]], ptr [[TMP17]], align 4
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i32> [[TMP11]], i32 3
+; CHECK-NEXT: store i32 [[TMP22]], ptr [[TMP18]], align 4
+; CHECK-NEXT: [[TMP23:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr nusw i64, ptr [[TMP23]], i32 0
+; CHECK-NEXT: store <4 x i64> [[TMP14]], ptr [[TMP24]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i64, ptr [[GEP_SRC_1]], align 4
+; CHECK-NEXT: [[LD_SRC_1_I32:%.*]] = trunc i64 [[LD_SRC_1]] to i32
+; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add i64 [[LD_SRC_1]], [[LD_SRC_2]]
+; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[IV]]
+; CHECK-NEXT: store i32 [[LD_SRC_1_I32]], ptr [[GEP_DST_1]], align 4
+; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[ADD]], ptr [[GEP_DST_2]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+
+ %gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv
+ %ld.src.1 = load i64, ptr %gep.src.1
+ %ld.src.1.i32 = trunc i64 %ld.src.1 to i32
+
+ %gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
+ %ld.src.2 = load i64, ptr %gep.src.2
+ %add = add i64 %ld.src.1, %ld.src.2
+
+ %gep.dst.1 = getelementptr nusw i64, ptr %dst.1, i64 %iv
+ store i32 %ld.src.1.i32, ptr %gep.dst.1
+
+ %gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
+ store i64 %add, ptr %gep.dst.2
+
+ %iv.next = add nuw nsw i64 %iv, 1
+ %cond = icmp ult i64 %iv.next, %n
+ br i1 %cond, label %loop, label %exit
+
+exit:
+ ret void
+}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+;.
>From 78e5e85f3506f29ec64d73a60496c17a3630c6ad Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Fri, 7 Mar 2025 17:02:20 +0000
Subject: [PATCH 2/2] [LV] Add two more tests
---
.../LoopVectorize/type-mismatch-interleave.ll | 209 +++++++++++++++++-
1 file changed, 205 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll b/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll
index 0b4ffc9e3008d..cdceee3fde097 100644
--- a/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll
+++ b/llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll
@@ -3,8 +3,10 @@
; Tests demonstrating that LV only ever interleaves when types mismatch.
-define void @different_types(ptr noalias %src.1, ptr noalias %src.2, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) {
-; CHECK-LABEL: define void @different_types(
+;; Tests where load type is different from store type.
+
+define void @load_store_type_mismatch(ptr noalias %src.1, ptr noalias %src.2, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) {
+; CHECK-LABEL: define void @load_store_type_mismatch(
; CHECK-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
@@ -98,8 +100,8 @@ exit:
ret void
}
-define void @different_types_rt_memcheck(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
-; CHECK-LABEL: define void @different_types_rt_memcheck(
+define void @load_store_type_mismatch_rt_memcheck(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
+; CHECK-LABEL: define void @load_store_type_mismatch_rt_memcheck(
; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[SRC_25:%.*]] = ptrtoint ptr [[SRC_2]] to i64
@@ -209,6 +211,190 @@ loop:
%cond = icmp ult i64 %iv.next, %n
br i1 %cond, label %loop, label %exit
+exit:
+ ret void
+}
+
+;; Tests with two load-store pairs of different types.
+
+define void @different_load_store_pairs(ptr noalias %src.1, ptr noalias %src.2, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) {
+; CHECK-LABEL: define void @different_load_store_pairs(
+; CHECK-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[TMP3]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr nusw i32, ptr [[DST_1]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr nusw i32, ptr [[TMP5]], i32 0
+; CHECK-NEXT: store <4 x i32> [[WIDE_LOAD]], ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr nusw i64, ptr [[TMP7]], i32 0
+; CHECK-NEXT: store <4 x i64> [[WIDE_LOAD1]], ptr [[TMP8]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i32, ptr [[GEP_SRC_1]], align 4
+; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
+; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i32, ptr [[DST_1]], i64 [[IV]]
+; CHECK-NEXT: store i32 [[LD_SRC_1]], ptr [[GEP_DST_1]], align 4
+; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[LD_SRC_2]], ptr [[GEP_DST_2]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+
+ %gep.src.1 = getelementptr i32, ptr %src.1, i64 %iv
+ %ld.src.1 = load i32, ptr %gep.src.1
+
+ %gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
+ %ld.src.2 = load i64, ptr %gep.src.2
+
+ %gep.dst.1 = getelementptr nusw i32, ptr %dst.1, i64 %iv
+ store i32 %ld.src.1, ptr %gep.dst.1
+
+ %gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
+ store i64 %ld.src.2, ptr %gep.dst.2
+
+ %iv.next = add nuw nsw i64 %iv, 1
+ %cond = icmp ult i64 %iv.next, %n
+ br i1 %cond, label %loop, label %exit
+
+exit:
+ ret void
+}
+
+define void @different_load_store_pairs_rt_memcheck(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
+; CHECK-LABEL: define void @different_load_store_pairs_rt_memcheck(
+; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[UMAX19:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX19]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
+; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[UMAX]], 2
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST_1]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[UMAX]], 3
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[DST_2]], i64 [[TMP1]]
+; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SRC_1]], i64 [[TMP0]]
+; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SRC_2]], i64 [[TMP1]]
+; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST_1]], [[SCEVGEP1]]
+; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[DST_2]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[DST_1]], [[SCEVGEP2]]
+; CHECK-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[SRC_1]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]]
+; CHECK-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[DST_1]], [[SCEVGEP3]]
+; CHECK-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[SRC_2]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]]
+; CHECK-NEXT: [[CONFLICT_RDX10:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT9]]
+; CHECK-NEXT: [[BOUND011:%.*]] = icmp ult ptr [[DST_2]], [[SCEVGEP2]]
+; CHECK-NEXT: [[BOUND112:%.*]] = icmp ult ptr [[SRC_1]], [[SCEVGEP1]]
+; CHECK-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]]
+; CHECK-NEXT: [[CONFLICT_RDX14:%.*]] = or i1 [[CONFLICT_RDX10]], [[FOUND_CONFLICT13]]
+; CHECK-NEXT: [[BOUND015:%.*]] = icmp ult ptr [[DST_2]], [[SCEVGEP3]]
+; CHECK-NEXT: [[BOUND116:%.*]] = icmp ult ptr [[SRC_2]], [[SCEVGEP1]]
+; CHECK-NEXT: [[FOUND_CONFLICT17:%.*]] = and i1 [[BOUND015]], [[BOUND116]]
+; CHECK-NEXT: [[CONFLICT_RDX18:%.*]] = or i1 [[CONFLICT_RDX14]], [[FOUND_CONFLICT17]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX18]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX19]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX19]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[TMP3]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4, !alias.scope [[META8:![0-9]+]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP5]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD20:%.*]] = load <4 x i64>, ptr [[TMP6]], align 4, !alias.scope [[META11:![0-9]+]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr nusw i32, ptr [[DST_1]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr nusw i32, ptr [[TMP7]], i32 0
+; CHECK-NEXT: store <4 x i32> [[WIDE_LOAD]], ptr [[TMP8]], align 4, !alias.scope [[META13:![0-9]+]], !noalias [[META15:![0-9]+]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr nusw i64, ptr [[TMP9]], i32 0
+; CHECK-NEXT: store <4 x i64> [[WIDE_LOAD20]], ptr [[TMP10]], align 4, !alias.scope [[META17:![0-9]+]], !noalias [[META18:![0-9]+]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX19]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i32, ptr [[GEP_SRC_1]], align 4
+; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
+; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i32, ptr [[DST_1]], i64 [[IV]]
+; CHECK-NEXT: store i32 [[LD_SRC_1]], ptr [[GEP_DST_1]], align 4
+; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
+; CHECK-NEXT: store i64 [[LD_SRC_2]], ptr [[GEP_DST_2]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP20:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+
+ %gep.src.1 = getelementptr i32, ptr %src.1, i64 %iv
+ %ld.src.1 = load i32, ptr %gep.src.1
+
+ %gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
+ %ld.src.2 = load i64, ptr %gep.src.2
+
+ %gep.dst.1 = getelementptr nusw i32, ptr %dst.1, i64 %iv
+ store i32 %ld.src.1, ptr %gep.dst.1
+
+ %gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
+ store i64 %ld.src.2, ptr %gep.dst.2
+
+ %iv.next = add nuw nsw i64 %iv, 1
+ %cond = icmp ult i64 %iv.next, %n
+ br i1 %cond, label %loop, label %exit
+
exit:
ret void
}
@@ -219,4 +405,19 @@ exit:
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
+; CHECK: [[META8]] = !{[[META9:![0-9]+]]}
+; CHECK: [[META9]] = distinct !{[[META9]], [[META10:![0-9]+]]}
+; CHECK: [[META10]] = distinct !{[[META10]], !"LVerDomain"}
+; CHECK: [[META11]] = !{[[META12:![0-9]+]]}
+; CHECK: [[META12]] = distinct !{[[META12]], [[META10]]}
+; CHECK: [[META13]] = !{[[META14:![0-9]+]]}
+; CHECK: [[META14]] = distinct !{[[META14]], [[META10]]}
+; CHECK: [[META15]] = !{[[META16:![0-9]+]], [[META9]], [[META12]]}
+; CHECK: [[META16]] = distinct !{[[META16]], [[META10]]}
+; CHECK: [[META17]] = !{[[META16]]}
+; CHECK: [[META18]] = !{[[META9]], [[META12]]}
+; CHECK: [[LOOP19]] = distinct !{[[LOOP19]], [[META1]], [[META2]]}
+; CHECK: [[LOOP20]] = distinct !{[[LOOP20]], [[META1]]}
;.
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