[llvm] [AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (PR #130302)

[Ivan Kosarev via llvm-commits]

https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/130302

These are encoded as 8-bit fields.

>From 065b7403b5bb200bffd927ab614d112c8031fb44 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Fri, 7 Mar 2025 16:12:07 +0000
Subject: [PATCH] [AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0
 operands.

These are encoded as 8-bit fields.
---
 .../Disassembler/AMDGPUDisassembler.cpp       | 34 +++++++++++--------
 .../Disassembler/AMDGPU/gfx11_dasm_sop1.txt   |  3 ++
 .../Disassembler/AMDGPU/gfx12_dasm_sop1.txt   |  3 ++
 3 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index afed8b999d8eb..728ce125eba2d 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -176,9 +176,12 @@ static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
 
 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
 // get register class. Used by SGPR only operands.
-#define DECODE_OPERAND_REG_7(RegClass, OpWidth)                                \
+#define DECODE_OPERAND_SREG_7(RegClass, OpWidth)                               \
   DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
 
+#define DECODE_OPERAND_SREG_8(RegClass, OpWidth)                               \
+  DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm, false, 0)
+
 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
@@ -270,20 +273,21 @@ DECODE_OPERAND_REG_8(VReg_384)
 DECODE_OPERAND_REG_8(VReg_512)
 DECODE_OPERAND_REG_8(VReg_1024)
 
-DECODE_OPERAND_REG_7(SReg_32, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XM0, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
-DECODE_OPERAND_REG_7(SReg_64, OPW64)
-DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
-DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64)
-DECODE_OPERAND_REG_7(SReg_96, OPW96)
-DECODE_OPERAND_REG_7(SReg_128, OPW128)
-DECODE_OPERAND_REG_7(SReg_128_XNULL, OPW128)
-DECODE_OPERAND_REG_7(SReg_256, OPW256)
-DECODE_OPERAND_REG_7(SReg_256_XNULL, OPW256)
-DECODE_OPERAND_REG_7(SReg_512, OPW512)
+DECODE_OPERAND_SREG_7(SReg_32, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XM0, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XEXEC, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, OPW32)
+DECODE_OPERAND_SREG_7(SReg_64_XEXEC, OPW64)
+DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, OPW64)
+DECODE_OPERAND_SREG_7(SReg_96, OPW96)
+DECODE_OPERAND_SREG_7(SReg_128, OPW128)
+DECODE_OPERAND_SREG_7(SReg_128_XNULL, OPW128)
+DECODE_OPERAND_SREG_7(SReg_256, OPW256)
+DECODE_OPERAND_SREG_7(SReg_256_XNULL, OPW256)
+DECODE_OPERAND_SREG_7(SReg_512, OPW512)
+
+DECODE_OPERAND_SREG_8(SReg_64, OPW64)
 
 DECODE_OPERAND_REG_8(AGPR_32)
 DECODE_OPERAND_REG_8(AReg_64)
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
index 291f348a35cc6..99a210b4ed088 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
@@ -2548,6 +2548,9 @@
 # GFX11: s_setpc_b64 vcc                         ; encoding: [0x6a,0x48,0x80,0xbe]
 0x6a,0x48,0x80,0xbe
 
+# GFX11: s_setpc_b64 -11/*Invalid immediate*/    ; encoding: [0xf5,0x48,0x80,0xbe]
+0xcb,0x48,0xf5,0xbe
+
 # GFX11: s_sext_i32_i16 exec_hi, s1              ; encoding: [0x01,0x0f,0xff,0xbe]
 0x01,0x0f,0xff,0xbe
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
index fa7d020bdd726..90528a97fa1df 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
@@ -3267,6 +3267,9 @@
 # GFX12: s_setpc_b64 vcc                         ; encoding: [0x6a,0x48,0x80,0xbe]
 0x6a,0x48,0x80,0xbe
 
+# GFX12: s_setpc_b64 -11/*Invalid immediate*/    ; encoding: [0xf5,0x48,0x80,0xbe]
+0xcb,0x48,0xf5,0xbe
+
 # GFX12: s_sext_i32_i16 exec_hi, s1              ; encoding: [0x01,0x0f,0xff,0xbe]
 0x01,0x0f,0xff,0xbe