[llvm] [X86] combineConcatVectorOps - recursively call combineConcatVectorOps instead of predicting when ops will freely concat (PR #130275)

[Simon Pilgrim via llvm-commits]

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@@ -58343,9 +58362,12 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
       if (!IsSplat && ((VT.is256BitVector() && Subtarget.hasInt256()) ||
                        (VT.is512BitVector() && Subtarget.useAVX512Regs() &&
                         (EltSizeInBits >= 32 || Subtarget.useBWIRegs())))) {
-        return DAG.getNode(Op0.getOpcode(), DL, VT,
-                           ConcatSubOperand(VT, Ops, 0),
-                           ConcatSubOperand(VT, Ops, 1));
+        SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
+        SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
+        if (Concat0 || Concat1)
+          return DAG.getNode(Op0.getOpcode(), DL, VT,
+                             Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
+                             Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 1));
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RKSimon wrote:

Yes - this case was always concatenating the binops even if there wasn't any benefit (there's a few similar ones to this that also need addressing) - I'm happy to remove this handling for now and just start with the FADD/FUB/MUL case to simplify the patch?

https://github.com/llvm/llvm-project/pull/130275