[llvm] SplitKit: Take register class directly from instruction definition (PR #129727)

[Mikael Holmén via llvm-commits]

mikaelholmen wrote:

> FWIW I suspect we have other constraint bugs somewhere. In principle this patch is making the code more conservative. Does your problem go away if you add a getCommonSubClass check to the use and def rc?

I'm happy to try something out but you'd need to be more specific about what and where in that case.

I reduced the problem down to a smallish mir-reproducer and from "-debug" printouts (with added LIS->dump() in RAGreedy::selectOrSplit) for that I see that we go from
```
176B	  %10:anh_0_7 = ldx_or_optionally_mv_nimm16_a16 0
[...]
288B	  nop implicit %10:anh_0_7
[...]
336B	  nop implicit %10:anh_0_7
[...]
496B	  dead %14:rn = COPY %10:anh_0_7
```
in the input to
```
176B	  dead %29:anh_0_7 = ldx_or_optionally_mv_nimm16_a16 0
[...]
232B	  %27:anh_0_7 = ldx_or_optionally_mv_nimm16_a16 0
[...]
280B	  %28:anh_rn = COPY %27:anh_0_7
288B	  nop implicit %28:anh_rn
[...]
328B	  %30:anh_rn = COPY %28:anh_rn
336B	  nop implicit %28:anh_rn
[...]
472B	  %32:anh_rn = COPY %30:anh_rn
[...]
496B	  dead %14:rn = COPY %32:anh_rn
```
which might still be correct, even if I don't understand why it has started using the register class "anh_rn" so much, but then after dealing with %30 we get
```
176B	  dead %29:anh_0_7 = ldx_or_optionally_mv_nimm16_a16 0
[...]
232B	  %27:anh_0_7 = ldx_or_optionally_mv_nimm16_a16 0
[...]
296B	  %28:anh_rn = COPY %27:anh_0_7
304B	  nop implicit %28:anh_rn
[...]
368B	  nop implicit %28:anh_rn
[...]
412B	  %46:anh_rn = ldx_or_optionally_mv_nimm16_a16 0
472B	  %32:anh_rn = COPY %46:anh_rn
[...]
512B	  dead %14:rn = COPY %32:anh_rn
```
and this is where the verifer protests on the %46 instruction since the ldx instruction should produce an "anh_0"_7 register and not "anh_rn".

Our machine has "a" and "r" registers and the "ldx" instruction can only write to "a" (i.e. "anh_0_7") registers and not to both "a" and "r" ("anh_rn").

(I've used "nop" instructions with implicit defs/uses as much as possible to get rid of our instruction set as much as I could in my reduced reproducer)

I also attached the regalloc log (with added LIS->dump()) in case that is interesting.
[bbi-104668_2.log.gz](https://github.com/user-attachments/files/19125491/bbi-104668_2.log.gz)


https://github.com/llvm/llvm-project/pull/129727