[llvm] AMDGPU: Handle demanded subvectors for readfirstlane (PR #128648)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b1` while building `llvm` at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/14398

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/ml-opt-rel-x86-64-b1/build/bin/opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes=instcombine < /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll | /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
+ /b/ml-opt-rel-x86-64-b1/build/bin/opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes=instcombine
+ /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll:373:15: error: CHECK-NEXT: expected string not found in input
; CHECK-NEXT: [[INS_1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>
              ^
<stdin>:191:55: note: scanning from here
 %1 = insertelement <4 x i32> poison, i32 %src0, i64 0
                                                      ^
<stdin>:191:55: note: with "TMP1" equal to "%1"
 %1 = insertelement <4 x i32> poison, i32 %src0, i64 0
                                                      ^
<stdin>:194:2: note: possible intended match here
 %4 = shufflevector <3 x i32> %3, <3 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 2>
 ^

Input file: <stdin>
Check file: /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
            .
            .
            .
          186: } 
          187:  
          188: ; Function Attrs: convergent 
          189: define <2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify1_convergencetoken(i32 %src0, i32 %src2) #1 { 
          190:  %t = call token @llvm.experimental.convergence.entry() 
          191:  %1 = insertelement <4 x i32> poison, i32 %src0, i64 0 
next:373'0                                                           X error: no match found
next:373'1                                                             with "TMP1" equal to "%1"
          192:  %2 = shufflevector <4 x i32> %1, <4 x i32> poison, <3 x i32> <i32 0, i32 poison, i32 0> 
next:373'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          193:  %3 = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> %2) [ "convergencectrl"(token %t) ] 
next:373'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          194:  %4 = shufflevector <3 x i32> %3, <3 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 2> 
next:373'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:373'2      ?                                                                                                    possible intended match
          195:  %shuffle = shufflevector <4 x i32> %4, <4 x i32> poison, <2 x i32> <i32 1, i32 3> 
next:373'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          196:  ret <2 x i32> %shuffle 
next:373'0     ~~~~~~~~~~~~~~~~~~~~~~~~
...

```

</details>

https://github.com/llvm/llvm-project/pull/128648