[llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)

[Jay Foad via llvm-commits]

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@@ -295,8 +295,21 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   getRegClassForOperandReg(const MachineRegisterInfo &MRI,
                            const MachineOperand &MO) const;
 
+  bool isVGPR(MCRegister Reg) const {
+    const TargetRegisterClass *RC = getPhysRegBaseClass(Reg);
+    // Registers without classes are unaddressable, SGPR-like registers.
+    return RC && isVGPRClass(RC);
+  }
   bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
+  bool isAGPR(MCRegister Reg) const {
+    const TargetRegisterClass *RC = getPhysRegBaseClass(Reg);
+    // Registers without classes are unaddressable, SGPR-like registers.
+    return RC && isAGPRClass(RC);
+  }
   bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
+  bool isVectorRegister(MCRegister Reg) const {
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jayfoad wrote:

Do we really need this? Can't we just use !isSGPRReg?

https://github.com/llvm/llvm-project/pull/128927