[llvm] support for the extension SPV_INTEL_fp_fast_math_mode (PR #130073)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 6 21:06:55 PST 2025
https://github.com/VishMCW updated https://github.com/llvm/llvm-project/pull/130073
>From 1ae83292e4b92517a1e045b69a13f9f6237af14f Mon Sep 17 00:00:00 2001
From: VishMCW <vishakh.prakash at multicorewareinc.com>
Date: Fri, 7 Mar 2025 10:06:48 +0530
Subject: [PATCH] Add support for extension SPV_INTEL_fp_fast_math_mode
---
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 5 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 23 ++++++--
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 3 ++
.../fp_contract_reassoc_fast_mode.ll | 52 +++++++++++++++++++
4 files changed, 78 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_fast_math_mode/fp_contract_reassoc_fast_mode.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 8d1714932c3c6..4c23e66fddc58 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "SPIRVCommandLine.h"
+#include "MCTargetDesc/SPIRVBaseInfo.h"
#include "llvm/ADT/StringRef.h"
#include <algorithm>
#include <map>
@@ -90,7 +91,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_KHR_non_semantic_info",
SPIRV::Extension::Extension::SPV_KHR_non_semantic_info},
{"SPV_INTEL_long_composites",
- SPIRV::Extension::Extension::SPV_INTEL_long_composites}};
+ SPIRV::Extension::Extension::SPV_INTEL_long_composites},
+ {"SPV_INTEL_fp_fast_math_mode",
+ SPIRV::Extension::Extension::SPV_INTEL_fp_fast_math_mode}};
bool SPIRVExtensionsParser::parse(cl::Option &O, llvm::StringRef ArgName,
llvm::StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index e0b348f0bba10..d7c3e9fb12a54 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1877,7 +1877,9 @@ static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI,
}
}
-static unsigned getFastMathFlags(const MachineInstr &I) {
+static unsigned getFastMathFlags(const MachineInstr &I,
+ const SPIRVSubtarget &ST,
+ SPIRV::RequirementHandler &Reqs) {
unsigned Flags = SPIRV::FPFastMathMode::None;
if (I.getFlag(MachineInstr::MIFlag::FmNoNans))
Flags |= SPIRV::FPFastMathMode::NotNaN;
@@ -1887,8 +1889,21 @@ static unsigned getFastMathFlags(const MachineInstr &I) {
Flags |= SPIRV::FPFastMathMode::NSZ;
if (I.getFlag(MachineInstr::MIFlag::FmArcp))
Flags |= SPIRV::FPFastMathMode::AllowRecip;
- if (I.getFlag(MachineInstr::MIFlag::FmReassoc))
- Flags |= SPIRV::FPFastMathMode::Fast;
+ if (I.getFlag(MachineInstr::MIFlag::FmReassoc)) {
+ if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_fp_fast_math_mode)) {
+ Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_fast_math_mode);
+ Reqs.addCapability(SPIRV::Capability::FPFastMathModeINTEL);
+ Flags |= SPIRV::FPFastMathMode::AllowReassoc;
+ } else
+ Flags |= SPIRV::FPFastMathMode::Fast;
+ }
+ if (I.getFlag(MachineInstr::MIFlag::FmContract))
+ if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_fp_fast_math_mode)) {
+ Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_fast_math_mode);
+ Reqs.addCapability(SPIRV::Capability::FPFastMathModeINTEL);
+ Flags |= SPIRV::FPFastMathMode::AllowContract;
+ }
+
return Flags;
}
@@ -1912,7 +1927,7 @@ static void handleMIFlagDecoration(MachineInstr &I, const SPIRVSubtarget &ST,
}
if (!TII.canUseFastMathFlags(I))
return;
- unsigned FMFlags = getFastMathFlags(I);
+ unsigned FMFlags = getFastMathFlags(I, ST, Reqs);
if (FMFlags == SPIRV::FPFastMathMode::None)
return;
Register DstReg = I.getOperand(0).getReg();
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index a871518e2094c..f9560afd10797 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -511,6 +511,7 @@ defm FunctionFloatControlINTEL : CapabilityOperand<5821, 0, 0, [SPV_INTEL_float_
defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composites], []>;
defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>;
defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
+defm FPFastMathModeINTEL : CapabilityOperand<5837, 0, 0, [SPV_INTEL_fp_fast_math_mode], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1050,6 +1051,8 @@ defm NotInf : FPFastMathModeOperand<0x2, [Kernel]>;
defm NSZ : FPFastMathModeOperand<0x4, [Kernel]>;
defm AllowRecip : FPFastMathModeOperand<0x8, [Kernel]>;
defm Fast : FPFastMathModeOperand<0x10, [Kernel]>;
+defm AllowContract : FPFastMathModeOperand<0x10000, [FPFastMathModeINTEL]>;
+defm AllowReassoc : FPFastMathModeOperand<0x20000, [FPFastMathModeINTEL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define FPRoundingMode enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_fast_math_mode/fp_contract_reassoc_fast_mode.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_fast_math_mode/fp_contract_reassoc_fast_mode.ll
new file mode 100644
index 0000000000000..700ee36b58faa
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_fast_math_mode/fp_contract_reassoc_fast_mode.ll
@@ -0,0 +1,52 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-EXT-OFF
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fp_fast_math_mode %s -o - | FileCheck %s --check-prefix=CHECK-EXT-ON
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_fp_fast_math_mode %s -o - -filetype=obj | spirv-val %}
+
+; CHECK-EXT-ON: OpCapability FPFastMathModeINTEL
+; CHECK-EXT-ON: SPV_INTEL_fp_fast_math_mode
+; CHECK-EXT-ON: OpName %[[#mul:]] "mul"
+; CHECK-EXT-ON: OpName %[[#sub:]] "sub"
+; CHECK-EXT-ON: OpDecorate %[[#mu:]] FPFastMathMode AllowContract
+; CHECK-EXT-ON: OpDecorate %[[#su:]] FPFastMathMode AllowReassoc
+
+; CHECK-EXT-OFF-NOT: OpCapability FPFastMathModeINTEL
+; CHECK-EXT-OFF-NOT: SPV_INTEL_fp_fast_math_mode
+; CHECK-EXT-OFF: OpName %[[#mul:]] "mul"
+; CHECK-EXT-OFF: OpName %[[#sub:]] "sub"
+; CHECK-EXT-OFF-NOT: 4 Decorate %[[#mul]] FPFastMathMode AllowContract
+; CHECK-EXT-OFF-NOT: 4 Decorate %[[#sub]] FPFastMathMode AllowReassoc
+
+
+; Function Attrs: convergent noinline norecurse nounwind optnone
+define spir_kernel void @test(float %a, float %b) #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+entry:
+ %a.addr = alloca float, align 4
+ %b.addr = alloca float, align 4
+ store float %a, ptr %a.addr, align 4
+ store float %b, ptr %b.addr, align 4
+ %0 = load float, ptr %a.addr, align 4
+ %1 = load float, ptr %a.addr, align 4
+ %mul = fmul contract float %0, %1
+ store float %mul, ptr %b.addr, align 4
+ %2 = load float, ptr %b.addr, align 4
+ %3 = load float, ptr %b.addr, align 4
+ %sub = fsub reassoc float %2, %3
+ store float %sub, ptr %b.addr, align 4
+ ret void
+}
+
+attributes #0 = { convergent noinline norecurse nounwind optnone "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{!"clang version 12.0.0 (https://github.com/intel/llvm.git 5cf8088c994778561c8584d5433d7d32618725b2)"}
+!3 = !{i32 0, i32 0}
+!4 = !{!"none", !"none"}
+!5 = !{!"float", !"float"}
+!6 = !{!"", !""}
+
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