[llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)

[Ivan Kosarev via llvm-commits]

================
@@ -165,6 +165,18 @@ enum VmemType {
   NUM_VMEM_TYPES
 };
 
+static unsigned getRegPoint(const GCNSubtarget &ST, MCRegister Reg,
+                            const SIRegisterInfo &TRI) {
+  // Order register interval points so that intervals of 32-bit VGPRs
+  // include intervals of their 16-bit halves.
+  MCRegister MCReg = AMDGPU::getMCReg(Reg, ST);
+  unsigned RegIdx = TRI.getHWRegIndex(MCReg);
+  bool IsHi = AMDGPU::isHi16Reg(MCReg, TRI);
+  bool IsVector = TRI.isVectorRegister(MCReg);
+  assert(isUInt<8>(RegIdx));
+  return (IsVector ? 0x200 : 0) | (RegIdx << 1) | (IsHi ? 1 : 0);
----------------
kosarev wrote:

I don't remember why the 0x200 bit in `getRegPoint()` was necessary back then, but since `getRegInterval()` itself makes sure the VGPR and SGPR ranges don't overlap, it seems the `(IsVector ? 0x200 : 0)` part can be dropped, thus making both the ranges start from 0 again.

https://github.com/llvm/llvm-project/pull/128927