[llvm] 81089f0 - [CodeGen] Use Register::id(). NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 6 09:12:02 PST 2025
Author: Craig Topper
Date: 2025-03-06T09:08:21-08:00
New Revision: 81089f0fd16e4eaae06f1a4be9611303c4f1cabf
URL: https://github.com/llvm/llvm-project/commit/81089f0fd16e4eaae06f1a4be9611303c4f1cabf
DIFF: https://github.com/llvm/llvm-project/commit/81089f0fd16e4eaae06f1a4be9611303c4f1cabf.diff
LOG: [CodeGen] Use Register::id(). NFC
Added:
Modified:
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
llvm/lib/CodeGen/LiveIntervalUnion.cpp
llvm/lib/CodeGen/LivePhysRegs.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MachineStableHash.cpp
llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
index e4bf77b6563a5..ae893176d0784 100644
--- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@@ -190,10 +190,10 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
// For now, only allow the register to be changed if its register
// class is consistent across all uses.
- if (!Classes[Reg] && NewRC)
- Classes[Reg] = NewRC;
- else if (!NewRC || Classes[Reg] != NewRC)
- Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
+ if (!Classes[Reg.id()] && NewRC)
+ Classes[Reg.id()] = NewRC;
+ else if (!NewRC || Classes[Reg.id()] != NewRC)
+ Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1);
// Now check for aliases.
for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
@@ -203,16 +203,16 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
unsigned AliasReg = (*AI).id();
if (Classes[AliasReg]) {
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
- Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
+ Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1);
}
}
// If we're still willing to consider this register, note the reference.
- if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
+ if (Classes[Reg.id()] != reinterpret_cast<TargetRegisterClass *>(-1))
RegRefs.insert(std::make_pair(Reg, &MO));
if (MO.isUse() && Special) {
- if (!KeepRegs.test(Reg)) {
+ if (!KeepRegs.test(Reg.id())) {
for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
KeepRegs.set(SubReg);
}
@@ -236,7 +236,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
// earlier instructions could still replace %eax even though the 'xor'
// itself can't be changed.
if (MI.isRegTiedToUseOperand(I) &&
- Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
+ Classes[Reg.id()] == reinterpret_cast<TargetRegisterClass *>(-1)) {
for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
KeepRegs.set(SubReg);
}
@@ -287,7 +287,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
// If we've already marked this reg as unchangeable, don't remove
// it or any of its subregs from KeepRegs.
- bool Keep = KeepRegs.test(Reg);
+ bool Keep = KeepRegs.test(Reg.id());
// For the reg itself and all subregs: update the def to current;
// reset the kill state, any restrictions, and references.
@@ -317,10 +317,10 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
// For now, only allow the register to be changed if its register
// class is consistent across all uses.
- if (!Classes[Reg] && NewRC)
- Classes[Reg] = NewRC;
- else if (!NewRC || Classes[Reg] != NewRC)
- Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
+ if (!Classes[Reg.id()] && NewRC)
+ Classes[Reg.id()] = NewRC;
+ else if (!NewRC || Classes[Reg.id()] != NewRC)
+ Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1);
RegRefs.insert(std::make_pair(Reg, &MO));
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index 0222069cfc576..fd89e40a5a1ee 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -385,7 +385,7 @@ GISelInstProfileBuilder::addNodeIDImmediate(int64_t Imm) const {
const GISelInstProfileBuilder &
GISelInstProfileBuilder::addNodeIDRegNum(Register Reg) const {
- ID.AddInteger(Reg);
+ ID.AddInteger(Reg.id());
return *this;
}
diff --git a/llvm/lib/CodeGen/LiveIntervalUnion.cpp b/llvm/lib/CodeGen/LiveIntervalUnion.cpp
index bfaa3bf9a694b..eb547c5238432 100644
--- a/llvm/lib/CodeGen/LiveIntervalUnion.cpp
+++ b/llvm/lib/CodeGen/LiveIntervalUnion.cpp
@@ -96,7 +96,7 @@ LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
// Verify the live intervals in this union and add them to the visited set.
void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
- VisitedVRegs.set(SI.value()->reg());
+ VisitedVRegs.set(SI.value()->reg().id());
}
#endif //!NDEBUG
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index f6b325a694d4f..7a06d108c66ca 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -90,7 +90,7 @@ void LivePhysRegs::stepForward(const MachineInstr &MI,
if (O->isDef()) {
// Note, dead defs are still recorded. The caller should decide how to
// handle them.
- Clobbers.push_back(std::make_pair(Reg, &*O));
+ Clobbers.push_back(std::make_pair(Reg.id(), &*O));
} else {
assert(O->isUse());
if (O->isKill())
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index cfdaacd1b86b2..4c1ff3f2d0dd4 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -253,9 +253,9 @@ LiveVariables::FindLastPartialDef(Register Reg,
/// implicit defs to a machine instruction if there was an earlier def of its
/// super-register.
void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
- MachineInstr *LastDef = PhysRegDef[Reg];
+ MachineInstr *LastDef = PhysRegDef[Reg.id()];
// If there was a previous use or a "full" def all is well.
- if (!LastDef && !PhysRegUse[Reg]) {
+ if (!LastDef && !PhysRegUse[Reg.id()]) {
// Otherwise, the last sub-register def implicitly defines this register.
// e.g.
// AH =
@@ -270,7 +270,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
if (LastPartialDef) {
LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
true/*IsImp*/));
- PhysRegDef[Reg] = LastPartialDef;
+ PhysRegDef[Reg.id()] = LastPartialDef;
SmallSet<MCPhysReg, 8> Processed;
for (MCPhysReg SubReg : TRI->subregs(Reg)) {
if (Processed.count(SubReg))
@@ -287,7 +287,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
Processed.insert(SS);
}
}
- } else if (LastDef && !PhysRegUse[Reg] &&
+ } else if (LastDef && !PhysRegUse[Reg.id()] &&
!LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
// Last def defines the super register, add an implicit def of reg.
LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
@@ -301,8 +301,8 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
/// FindLastRefOrPartRef - Return the last reference or partial reference of
/// the specified register.
MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
- MachineInstr *LastDef = PhysRegDef[Reg];
- MachineInstr *LastUse = PhysRegUse[Reg];
+ MachineInstr *LastDef = PhysRegDef[Reg.id()];
+ MachineInstr *LastUse = PhysRegUse[Reg.id()];
if (!LastDef && !LastUse)
return nullptr;
@@ -330,8 +330,8 @@ MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
}
bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
- MachineInstr *LastDef = PhysRegDef[Reg];
- MachineInstr *LastUse = PhysRegUse[Reg];
+ MachineInstr *LastDef = PhysRegDef[Reg.id()];
+ MachineInstr *LastUse = PhysRegUse[Reg.id()];
if (!LastDef && !LastUse)
return false;
@@ -380,27 +380,27 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
}
}
- if (!PhysRegUse[Reg]) {
+ if (!PhysRegUse[Reg.id()]) {
// Partial uses. Mark register def dead and add implicit def of
// sub-registers which are used.
// dead EAX = op implicit-def AL
// That is, EAX def is dead but AL def extends pass it.
- PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
+ PhysRegDef[Reg.id()]->addRegisterDead(Reg, TRI, true);
for (MCPhysReg SubReg : TRI->subregs(Reg)) {
if (!PartUses.count(SubReg))
continue;
bool NeedDef = true;
- if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
- MachineOperand *MO =
- PhysRegDef[Reg]->findRegisterDefOperand(SubReg, /*TRI=*/nullptr);
+ if (PhysRegDef[Reg.id()] == PhysRegDef[SubReg]) {
+ MachineOperand *MO = PhysRegDef[Reg.id()]->findRegisterDefOperand(
+ SubReg, /*TRI=*/nullptr);
if (MO) {
NeedDef = false;
assert(!MO->isDead());
}
}
if (NeedDef)
- PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
- true/*IsDef*/, true/*IsImp*/));
+ PhysRegDef[Reg.id()]->addOperand(
+ MachineOperand::CreateReg(SubReg, true /*IsDef*/, true /*IsImp*/));
MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
if (LastSubRef)
LastSubRef->addRegisterKilled(SubReg, TRI, true);
@@ -412,7 +412,8 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
for (MCPhysReg SS : TRI->subregs(SubReg))
PartUses.erase(SS);
}
- } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
+ } else if (LastRefOrPartRef == PhysRegDef[Reg.id()] &&
+ LastRefOrPartRef != MI) {
if (LastPartDef)
// The last partial def kills the register.
LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
@@ -463,7 +464,7 @@ void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,
SmallVectorImpl<Register> &Defs) {
// What parts of the register are previously defined?
SmallSet<unsigned, 32> Live;
- if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
+ if (PhysRegDef[Reg.id()] || PhysRegUse[Reg.id()]) {
for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
Live.insert(SubReg);
} else {
diff --git a/llvm/lib/CodeGen/MachineStableHash.cpp b/llvm/lib/CodeGen/MachineStableHash.cpp
index 5ab589acee413..9d56696079478 100644
--- a/llvm/lib/CodeGen/MachineStableHash.cpp
+++ b/llvm/lib/CodeGen/MachineStableHash.cpp
@@ -68,7 +68,7 @@ stable_hash llvm::stableHashValue(const MachineOperand &MO) {
}
// Register operands don't have target flags.
- return stable_hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
+ return stable_hash_combine(MO.getType(), MO.getReg().id(), MO.getSubReg(),
MO.isDef());
case MachineOperand::MO_Immediate:
return stable_hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
index 5784974cd8ed9..be73b73c93989 100644
--- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
+++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
@@ -180,5 +180,5 @@ TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF) const {
TargetFrameLowering::DwarfFrameBase
TargetFrameLowering::getDwarfFrameBase(const MachineFunction &MF) const {
const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
- return DwarfFrameBase{DwarfFrameBase::Register, {RI->getFrameRegister(MF)}};
+ return DwarfFrameBase{DwarfFrameBase::Register, {RI->getFrameRegister(MF).id()}};
}
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 3fe8d5dbc4b67..599640018c597 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -498,7 +498,7 @@ bool TargetRegisterInfo::getRegAllocationHints(
continue;
// All clear, tell the register allocator to prefer this register.
- Hints.push_back(Phys);
+ Hints.push_back(Phys.id());
}
return false;
}
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