[llvm] d0b8f5d - [RegisterBankInfo] Use MCRegister instead of Register for getMinimalPhysRegClass. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-03-06T09:07:53-08:00
New Revision: d0b8f5d8b3e11b283695558c3bcdea7629e9838b

URL: https://github.com/llvm/llvm-project/commit/d0b8f5d8b3e11b283695558c3bcdea7629e9838b
DIFF: https://github.com/llvm/llvm-project/commit/d0b8f5d8b3e11b283695558c3bcdea7629e9838b.diff

LOG: [RegisterBankInfo] Use MCRegister instead of Register for getMinimalPhysRegClass. NFC

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/RegisterBankInfo.h
    llvm/lib/CodeGen/RegisterBankInfo.cpp

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/RegisterBankInfo.h
index 9704e3b1fdedd..a4f3052b5bca7 100644
--- a/llvm/include/llvm/CodeGen/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterBankInfo.h
@@ -419,7 +419,7 @@ class RegisterBankInfo {
 
   /// Getting the minimal register class of a physreg is expensive.
   /// Cache this information as we get it.
-  mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs;
+  mutable DenseMap<MCRegister, const TargetRegisterClass *> PhysRegMinimalRCs;
 
   /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
   /// RegisterBank instances.
@@ -445,7 +445,7 @@ class RegisterBankInfo {
   /// Get the MinimalPhysRegClass for Reg.
   /// \pre Reg is a physical register.
   const TargetRegisterClass *
-  getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const;
+  getMinimalPhysRegClass(MCRegister Reg, const TargetRegisterInfo &TRI) const;
 
   /// Try to get the mapping of \p MI.
   /// See getInstrMapping for more details on what a mapping represents.

diff  --git a/llvm/lib/CodeGen/RegisterBankInfo.cpp b/llvm/lib/CodeGen/RegisterBankInfo.cpp
index e1720b038e236..a0061ece8add6 100644
--- a/llvm/lib/CodeGen/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterBankInfo.cpp
@@ -100,9 +100,8 @@ RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
 }
 
 const TargetRegisterClass *
-RegisterBankInfo::getMinimalPhysRegClass(Register Reg,
+RegisterBankInfo::getMinimalPhysRegClass(MCRegister Reg,
                                          const TargetRegisterInfo &TRI) const {
-  assert(Reg.isPhysical() && "Reg must be a physreg");
   const auto [RegRCIt, Inserted] = PhysRegMinimalRCs.try_emplace(Reg);
   if (Inserted)
     RegRCIt->second = TRI.getMinimalPhysRegClassLLT(Reg, LLT());