[llvm] [AMDGPU][GISel] Add 64bit pattern to emit `v_lshl_add_u64` (PR #124763)

[Alan Li via llvm-commits]

================
@@ -762,15 +762,27 @@ def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>;
 def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>;
 def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>;
 
+let SubtargetPredicate = HasLShlAddB64 in {
+// TODO: Canonicalize these in the target specific CombinerHelper?
 def : GCNPat<
- (DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
- (V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
+  (ptradd (shl i64:$src0, i32:$shift), i64:$src1),
----------------
lialan wrote:

yeah the change is misaligned by git. Only 2 new patterns are added in this PR:

```
def : GCNPat<
  (ptradd (shl i64:$src0, i32:$shift), i64:$src1),
  (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$shift, VSrc_b64:$src1)
>;

def : GCNPat<
  (ptradd i64:$src0, (shl i64:$src1, i32:$shift)),
  (V_LSHL_ADD_U64_e64 VSrc_b64:$src1, VSrc_b32:$shift, VSrc_b64:$src0)
>;
``` 

https://github.com/llvm/llvm-project/pull/124763