[llvm] AMDGPU: Add pseudoinstruction for agpr or vgpr constants (PR #130042)

[Joe Nash via llvm-commits]

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@@ -140,6 +140,25 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
   let UseNamedOperandTable = 1;
 }
 
+// 32-bit materialize immediate which supports AGPR or VGPR. Typically
+// this should just expand to V_MOV_B32, unless $vdst happens to be
+// allocated to an AGPR in which case it will lower to
+// V_ACCVGPR_WRITE_B32. This should always use an inline immediate
+// operand, as v_accvgpr_write_b32 does not support literal constants.
+def AV_MOV_B32_IMM_PSEUDO
+    : VPseudoInstSI<(outs AV_32:$vdst), (ins VCSrc_b32:$src0)> {
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Sisyph wrote:

Can you create a AVDst_32 for the dst type? I'm trying to use a RegisterOperand instead of RegisterClass for all operands in instruction definitions because it makes it easier to swap out the underlying RegisterClass. 

https://github.com/llvm/llvm-project/pull/130042