[llvm] PowerPC: Use REG_SEQUENCE instead of INSERT_SUBREG (PR #129941)

via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 6 06:32:48 PST 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-powerpc

Author: Lei Huang (lei137)

<details>
<summary>Changes</summary>

Update to use REG_SEQUENCE when possible.

This patch only update td pattern to utilize REG_SEQUENCE for INSERT_SUBREG for cases where it does not produce
a nesting  of REG_SEQUENCE.  This seem to show some improvement in code gen for `llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll`.   

Fixes part of https://github.com/llvm/llvm-project/issues/125502


---

Patch is 79.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/129941.diff


13 Files Affected:

- (modified) llvm/lib/Target/PowerPC/PPCInstrMMA.td (+12-13) 
- (modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (+2-8) 
- (modified) llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll (+32-32) 
- (modified) llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll (+6-6) 
- (modified) llvm/test/CodeGen/PowerPC/mma-acc-memops.ll (+28-28) 
- (modified) llvm/test/CodeGen/PowerPC/mma-acc-spill.ll (+2-2) 
- (modified) llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll (+16-16) 
- (modified) llvm/test/CodeGen/PowerPC/mma-intrinsics.ll (+16-16) 
- (modified) llvm/test/CodeGen/PowerPC/mma-outer-product.ll (+160-160) 
- (modified) llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll (+12-24) 
- (modified) llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll (+8-8) 
- (modified) llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll (+1-1) 
- (modified) llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll (+48-46) 


``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrMMA.td b/llvm/lib/Target/PowerPC/PPCInstrMMA.td
index 161d4d3c492f3..c40d3996dd181 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrMMA.td
@@ -1055,19 +1055,18 @@ let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
 }
 
 def ConcatsMMA {
-  dag VecsToVecPair0 =
-    (v256i1 (INSERT_SUBREG
-      (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
-      $vs1, sub_vsx0));
-  dag VecsToVecPair1 =
-    (v256i1 (INSERT_SUBREG
-      (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
-      $vs3, sub_vsx0));
-  dag VecsToVecQuad =
-    (BUILD_UACC (INSERT_SUBREG
-                  (INSERT_SUBREG (v512i1 (IMPLICIT_DEF)),
-                                 (KILL_PAIR VecsToVecPair0), sub_pair0),
-                  (KILL_PAIR VecsToVecPair1), sub_pair1));
+   dag VecsToVecPair0 =
+          (v256i1 (INSERT_SUBREG
+                    (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
+                    $vs1, sub_vsx0));
+   dag VecsToVecPair1 =
+          (v256i1 (INSERT_SUBREG
+                    (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
+                    $vs3, sub_vsx0));
+  dag VecsToVecQuad = (BUILD_UACC
+          (v512i1 (REG_SEQUENCE UACCRC,
+                                (KILL_PAIR VecsToVecPair0), sub_pair0,
+                                (KILL_PAIR VecsToVecPair1), sub_pair1)));
 }
 
 def Extracts {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 19247c1f3fe6d..39a1ab0d388a7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -1139,17 +1139,11 @@ class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
   let Inst{63} = 0;
 }
 
-
-
 def Concats {
   dag VecsToVecPair0 =
-    (v256i1 (INSERT_SUBREG
-      (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
-      $vs1, sub_vsx0));
+    (v256i1 (REG_SEQUENCE VSRpRC, $vs0, sub_vsx1, $vs1, sub_vsx0));
   dag VecsToVecPair1 =
-    (v256i1 (INSERT_SUBREG
-      (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
-      $vs3, sub_vsx0));
+    (v256i1 (REG_SEQUENCE VSRpRC, $vs2, sub_vsx1, $vs3, sub_vsx0));
 }
 
 let Predicates = [PairedVectorMemops] in {
diff --git a/llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll b/llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll
index 881e563ec915a..2a3ae4f6a5007 100644
--- a/llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll
@@ -70,10 +70,10 @@ declare <512 x i1> @llvm.ppc.mma.pmxvbf16ger2(<16 x i8>, <16 x i8>, i32, i32, i3
 define dso_local void @test52(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test52:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvbf16ger2pp acc0, v2, v2
 ; CHECK-NEXT:    xxmfacc acc0
@@ -85,10 +85,10 @@ define dso_local void @test52(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test52:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvbf16ger2pp acc0, v2, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -111,10 +111,10 @@ declare <512 x i1> @llvm.ppc.mma.xvbf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
 define dso_local void @test53(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test53:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvbf16ger2pn acc0, v2, v2
 ; CHECK-NEXT:    xxmfacc acc0
@@ -126,10 +126,10 @@ define dso_local void @test53(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test53:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvbf16ger2pn acc0, v2, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -152,10 +152,10 @@ declare <512 x i1> @llvm.ppc.mma.xvbf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>)
 define dso_local void @test54(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test54:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvbf16ger2np acc0, v2, v2
 ; CHECK-NEXT:    xxmfacc acc0
@@ -167,10 +167,10 @@ define dso_local void @test54(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test54:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvbf16ger2np acc0, v2, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -193,10 +193,10 @@ declare <512 x i1> @llvm.ppc.mma.xvbf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>)
 define dso_local void @test55(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test55:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvbf16ger2nn acc0, v2, v2
 ; CHECK-NEXT:    xxmfacc acc0
@@ -208,10 +208,10 @@ define dso_local void @test55(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test55:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvbf16ger2nn acc0, v2, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -234,10 +234,10 @@ declare <512 x i1> @llvm.ppc.mma.xvbf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>)
 define dso_local void @test56(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test56:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    pmxvbf16ger2pp acc0, v2, v2, 0, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
@@ -249,10 +249,10 @@ define dso_local void @test56(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test56:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    pmxvbf16ger2pp acc0, v2, v2, 0, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -275,10 +275,10 @@ declare <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>
 define dso_local void @test57(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test57:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    pmxvbf16ger2pn acc0, v2, v2, 0, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
@@ -290,10 +290,10 @@ define dso_local void @test57(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test57:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    pmxvbf16ger2pn acc0, v2, v2, 0, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -316,10 +316,10 @@ declare <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>
 define dso_local void @test58(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test58:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    pmxvbf16ger2np acc0, v2, v2, 0, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
@@ -331,10 +331,10 @@ define dso_local void @test58(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test58:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    pmxvbf16ger2np acc0, v2, v2, 0, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
@@ -357,10 +357,10 @@ declare <512 x i1> @llvm.ppc.mma.pmxvbf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>
 define dso_local void @test59(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
 ; CHECK-LABEL: test59:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 32(r3)
-; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
+; CHECK-NEXT:    lxv vs1, 32(r3)
+; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    pmxvbf16ger2nn acc0, v2, v2, 0, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
@@ -372,10 +372,10 @@ define dso_local void @test59(ptr nocapture readonly %vqp, ptr nocapture readnon
 ;
 ; CHECK-BE-LABEL: test59:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    pmxvbf16ger2nn acc0, v2, v2, 0, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll b/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
index 5decd9a639af8..7e2f744ac1d71 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
@@ -28,9 +28,9 @@ define void @testMultiply(ptr nocapture noundef readonly %a, ptr nocapture nound
 ; CHECK-NEXT:    bl _Z15buildVectorPairPu13__vector_pairDv16_hS0_ at notoc
 ; CHECK-NEXT:    xxsetaccz acc1
 ; CHECK-NEXT:    xvf32gerpp acc1, v31, v30
-; CHECK-NEXT:    lxv v3, 32(r1)
 ; CHECK-NEXT:    lxv vs0, 48(r1)
-; CHECK-NEXT:    xvf32gerpp acc1, v3, vs0
+; CHECK-NEXT:    lxv vs1, 32(r1)
+; CHECK-NEXT:    xvf32gerpp acc1, vs1, vs0
 ; CHECK-NEXT:    lxv v31, -48(r30) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v30, -64(r30) # 16-byte Folded Reload
 ; CHECK-NEXT:    xxmfacc acc1
@@ -71,16 +71,16 @@ define void @testMultiply(ptr nocapture noundef readonly %a, ptr nocapture nound
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    xxsetaccz acc1
 ; CHECK-BE-NEXT:    xvf32gerpp acc1, v31, v30
-; CHECK-BE-NEXT:    lxv v3, 144(r1)
 ; CHECK-BE-NEXT:    lxv vs0, 128(r1)
-; CHECK-BE-NEXT:    xvf32gerpp acc1, vs0, v3
+; CHECK-BE-NEXT:    lxv vs1, 144(r1)
+; CHECK-BE-NEXT:    xvf32gerpp acc1, vs0, vs1
 ; CHECK-BE-NEXT:    lxv v31, -48(r30) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v30, -64(r30) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    xxmfacc acc1
-; CHECK-BE-NEXT:    xxlor vs1, vs6, vs6
-; CHECK-BE-NEXT:    xxlor vs0, vs7, vs7
 ; CHECK-BE-NEXT:    xxlor vs3, vs4, vs4
 ; CHECK-BE-NEXT:    xxlor vs2, vs5, vs5
+; CHECK-BE-NEXT:    xxlor vs1, vs6, vs6
+; CHECK-BE-NEXT:    xxlor vs0, vs7, vs7
 ; CHECK-BE-NEXT:    stxv vs0, 0(r29)
 ; CHECK-BE-NEXT:    pstxv vs1, 8(r29), 0
 ; CHECK-BE-NEXT:    stxv vs2, 16(r29)
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
index 31ddc619d9762..059d60a9608f8 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -26,10 +26,10 @@
 define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testLdSt:
 ; LE-PAIRED:       # %bb.0: # %entry
-; LE-PAIRED-NEXT:    plxv vs1, f at PCREL+96(0), 1
-; LE-PAIRED-NEXT:    plxv vs0, f at PCREL+112(0), 1
 ; LE-PAIRED-NEXT:    plxv vs3, f at PCREL+64(0), 1
 ; LE-PAIRED-NEXT:    plxv vs2, f at PCREL+80(0), 1
+; LE-PAIRED-NEXT:    plxv vs1, f at PCREL+96(0), 1
+; LE-PAIRED-NEXT:    plxv vs0, f at PCREL+112(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs0, f at PCREL+176(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs1, f at PCREL+160(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs2, f at PCREL+144(0), 1
@@ -40,10 +40,10 @@ define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, f at toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, f at toc@l
-; BE-PAIRED-NEXT:    lxv vs1, 80(r3)
-; BE-PAIRED-NEXT:    lxv vs0, 64(r3)
 ; BE-PAIRED-NEXT:    lxv vs3, 112(r3)
 ; BE-PAIRED-NEXT:    lxv vs2, 96(r3)
+; BE-PAIRED-NEXT:    lxv vs1, 80(r3)
+; BE-PAIRED-NEXT:    lxv vs0, 64(r3)
 ; BE-PAIRED-NEXT:    stxv vs1, 144(r3)
 ; BE-PAIRED-NEXT:    stxv vs0, 128(r3)
 ; BE-PAIRED-NEXT:    stxv vs3, 176(r3)
@@ -135,12 +135,12 @@ define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-NEXT:    paddi r5, 0, f at PCREL, 1
 ; LE-PAIRED-NEXT:    sldi r3, r3, 6
 ; LE-PAIRED-NEXT:    add r6, r5, r3
-; LE-PAIRED-NEXT:    lxv vs1, 32(r6)
-; LE-PAIRED-NEXT:    lxv vs0, 48(r6)
 ; LE-PAIRED-NEXT:    lxvx vs3, r5, r3
-; LE-PAIRED-NEXT:    lxv vs2, 16(r6)
 ; LE-PAIRED-NEXT:    sldi r3, r4, 6
 ; LE-PAIRED-NEXT:    add r4, r5, r3
+; LE-PAIRED-NEXT:    lxv vs2, 16(r6)
+; LE-PAIRED-NEXT:    lxv vs1, 32(r6)
+; LE-PAIRED-NEXT:    lxv vs0, 48(r6)
 ; LE-PAIRED-NEXT:    stxvx vs3, r5, r3
 ; LE-PAIRED-NEXT:    stxv vs0, 48(r4)
 ; LE-PAIRED-NEXT:    stxv vs1, 32(r4)
@@ -153,12 +153,12 @@ define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PAIRED-NEXT:    addi r5, r5, f at toc@l
 ; BE-PAIRED-NEXT:    sldi r3, r3, 6
 ; BE-PAIRED-NEXT:    add r6, r5, r3
+; BE-PAIRED-NEXT:    lxv vs3, 48(r6)
+; BE-PAIRED-NEXT:    lxv vs2, 32(r6)
 ; BE-PAIRED-NEXT:    lxvx vs0, r5, r3
+; BE-PAIRED-NEXT:    lxv vs1, 16(r6)
 ; BE-PAIRED-NEXT:    sldi r3, r4, 6
 ; BE-PAIRED-NEXT:    add r4, r5, r3
-; BE-PAIRED-NEXT:    lxv vs1, 16(r6)
-; BE-PAIRED-NEXT:    lxv vs3, 48(r6)
-; BE-PAIRED-NEXT:    lxv vs2, 32(r6)
 ; BE-PAIRED-NEXT:    stxvx vs0, r5, r3
 ; BE-PAIRED-NEXT:    stxv vs1, 16(r4)
 ; BE-PAIRED-NEXT:    stxv vs3, 48(r4)
@@ -253,10 +253,10 @@ entry:
 define dso_local void @testUnalignedLdSt() {
 ; LE-PAIRED-LABEL: testUnalignedLdSt:
 ; LE-PAIRED:       # %bb.0: # %entry
-; LE-PAIRED-NEXT:    plxv vs1, f at PCREL+43(0), 1
-; LE-PAIRED-NEXT:    plxv vs0, f at PCREL+59(0), 1
 ; LE-PAIRED-NEXT:    plxv vs3, f at PCREL+11(0), 1
 ; LE-PAIRED-NEXT:    plxv vs2, f at PCREL+27(0), 1
+; LE-PAIRED-NEXT:    plxv vs1, f at PCREL+43(0), 1
+; LE-PAIRED-NEXT:    plxv vs0, f at PCREL+59(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs0, f at PCREL+67(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs1, f at PCREL+51(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs2, f at PCREL+35(0), 1
@@ -267,10 +267,10 @@ define dso_local void @testUnalignedLdSt() {
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, f at toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, f at toc@l
-; BE-PAIRED-NEXT:    plxv vs1, 27(r3), 0
-; BE-PAIRED-NEXT:    plxv vs0, 11(r3), 0
 ; BE-PAIRED-NEXT:    plxv vs3, 59(r3), 0
 ; BE-PAIRED-NEXT:    plxv vs2, 43(r3), 0
+; BE-PAIRED-NEXT:    plxv vs1, 27(r3), 0
+; BE-PAIRED-NEXT:    plxv vs0, 11(r3), 0
 ; BE-PAIRED-NEXT:    pstxv vs1, 35(r3), 0
 ; BE-PAIRED-NEXT:    pstxv vs0, 19(r3), 0
 ; BE-PAIRED-NEXT:    pstxv vs3, 67(r3), 0
@@ -375,19 +375,19 @@ entry:
 define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
-; LE-PAIRED-NEXT:    plxv v3, g at PCREL+32(0), 1
 ; LE-PAIRED-NEXT:    plxv vs0, g at PCREL+48(0), 1
+; LE-PAIRED-NEXT:    plxv vs1, g at PCREL+32(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs0, g at PCREL+80(0), 1
-; LE-PAIRED-NEXT:    pstxv v3, g at PCREL+64(0), 1
+; LE-PAIRED-NEXT:    pstxv vs1, g at PCREL+64(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, g at toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, g at toc@l
-; BE-PAIRED-NEXT:    lxv v3, 48(r3)
 ; BE-PAIRED-NEXT:    lxv vs0, 32(r3)
-; BE-PAIRED-NEXT:    stxv v3, 80(r3)
+; BE-PAIRED-NEXT:    lxv vs1, 48(r3)
+; BE-PAIRED-NEXT:    stxv vs1, 80(r3)
 ; BE-PAIRED-NEXT:    stxv vs0, 64(r3)
 ; BE-PAIRED-NEXT:    blr
 ;
@@ -452,12 +452,12 @@ define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-NEXT:    sldi r3, r3, 5
 ; LE-PAIRED-NEXT:    paddi r5, 0, g at PCREL, 1
 ; LE-PAIRED-NEXT:    add r6, r5, r3
-; LE-PAIRED-NEXT:    lxvx v3, r5, r3
+; LE-PAIRED-NEXT:    lxvx vs0, r5, r3
 ; LE-PAIRED-NEXT:    sldi r3, r4, 5
 ; LE-PAIRED-NEXT:    add r4, r5, r3
-; LE-PAIRED-NEXT:    lxv vs0, 16(r6)
-; LE-PAIRED-NEXT:    stxvx v3, r5, r3
-; LE-PAIRED-NEXT:    stxv vs0, 16(r4)
+; LE-PAIRED-NEXT:    lxv vs1, 16(r6)
+; LE-PAIRED-NEXT:    stxvx vs0, r5, r3
+; LE-PAIRED-NEXT:    stxv vs1, 16(r4)
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testXLdStPair:
@@ -469,9 +469,9 @@ define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PAIRED-NEXT:    lxvx vs0, r5, r3
 ; BE-PAIRED-NEXT:    sldi r3, r4, 5
 ; BE-PAIRED-NEXT:    add r4, r5, r3
-; BE-PAIRED-NEXT:    lxv v3, 16(r6)
+; BE-PAIRED-NEXT:    lxv vs1, 16(r6)
 ; BE-PAIRED-NEXT:    stxvx vs0, r5, r3
-; BE-PAIRED-NEXT:    stxv v3, 16(r4)
+; BE-PAIRED-NEXT:    stxv vs1, 16(r4)
 ; BE-PAIRED-NEXT:    blr
 ;
 ; LE-PWR9-LABEL: testXLdStPair:
@@ -542,19 +542,19 @@ entry:
 define dso_local void @testUnalignedLdStPair() {
 ; LE-PAIRED-LABEL: testUnalignedLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
-; LE-PAIRED-NEXT:    plxv v3, g at PCREL+11(0), 1
 ; LE-PAIRED-NEXT:    plxv vs0, g at PCREL+27(0), 1
+; LE-PAIRED-NEXT:    plxv vs1, g at PCREL+11(0), 1
 ; LE-PAIRED-NEXT:    pstxv vs0, g at PCREL+35(0), 1
-; LE-PAIRED-NEXT:    pstxv v3, g at PCREL+19(0), 1
+; LE-PAIRED-NEXT:    pstxv vs1, g at PCREL+19(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testUnalignedLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, g at toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, g at toc@l
-; BE-PAIRED-NEXT:    plxv v3, 27(r3), 0
 ; BE-PAIRED-NEXT:    plxv vs0, 11(r3), 0
-; BE-PAIRED-NEXT:    pstxv v3, 35(r3), 0
+; BE-PAIRED-NEXT:    plxv vs1, 27(r3), 0
+; BE-PAIRED-NEXT:    pstxv vs1, 35(r3), 0
 ; BE-PAIRED-NEXT:    pstxv vs0, 19(r3), 0
 ; BE-PAIRED-NEXT:    blr
 ;
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
index 681f81d74794d..abc65bed5bf6c 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
@@ -38,9 +38,9 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
 ; CHECK-NEXT:    stxv v31, 144(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    vmr v31, v5
 ; CHECK-NEX...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/129941


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