[llvm] [RISCV][LibCall] Add libcall for i64 -> bf16 (PR #130024)
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 6 01:19:29 PST 2025
https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/130024
Add support for lowering i64 -> bf16 with libcall.
>From 0f3b10e069692c726d5c8ec80a65bc71b6cd0977 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Thu, 6 Mar 2025 14:37:24 +0800
Subject: [PATCH] [RISCV][LibCall] Add libcall for i64 -> bf16
Add support for lowering i64 -> bf16 with libcall.
---
llvm/include/llvm/IR/RuntimeLibcalls.def | 2 +
llvm/lib/CodeGen/TargetLoweringBase.cpp | 4 +
llvm/test/CodeGen/RISCV/bfloat-convert.ll | 102 +++++++++++++++++++---
3 files changed, 98 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
index c6ac341d71a20..2545aebc73391 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.def
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -444,6 +444,7 @@ HANDLE_LIBCALL(SINTTOFP_I32_F64, "__floatsidf")
HANDLE_LIBCALL(SINTTOFP_I32_F80, "__floatsixf")
HANDLE_LIBCALL(SINTTOFP_I32_F128, "__floatsitf")
HANDLE_LIBCALL(SINTTOFP_I32_PPCF128, "__gcc_itoq")
+HANDLE_LIBCALL(SINTTOFP_I64_BF16, "__floatdibf")
HANDLE_LIBCALL(SINTTOFP_I64_F16, "__floatdihf")
HANDLE_LIBCALL(SINTTOFP_I64_F32, "__floatdisf")
HANDLE_LIBCALL(SINTTOFP_I64_F64, "__floatdidf")
@@ -462,6 +463,7 @@ HANDLE_LIBCALL(UINTTOFP_I32_F64, "__floatunsidf")
HANDLE_LIBCALL(UINTTOFP_I32_F80, "__floatunsixf")
HANDLE_LIBCALL(UINTTOFP_I32_F128, "__floatunsitf")
HANDLE_LIBCALL(UINTTOFP_I32_PPCF128, "__gcc_utoq")
+HANDLE_LIBCALL(UINTTOFP_I64_BF16, "__floatundibf")
HANDLE_LIBCALL(UINTTOFP_I64_F16, "__floatundihf")
HANDLE_LIBCALL(UINTTOFP_I64_F32, "__floatundisf")
HANDLE_LIBCALL(UINTTOFP_I64_F64, "__floatundidf")
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index f5ea3c0b47d6a..3da66a4113334 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -312,6 +312,8 @@ RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
if (RetVT == MVT::ppcf128)
return SINTTOFP_I32_PPCF128;
} else if (OpVT == MVT::i64) {
+ if (RetVT == MVT::bf16)
+ return SINTTOFP_I64_BF16;
if (RetVT == MVT::f16)
return SINTTOFP_I64_F16;
if (RetVT == MVT::f32)
@@ -358,6 +360,8 @@ RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
if (RetVT == MVT::ppcf128)
return UINTTOFP_I32_PPCF128;
} else if (OpVT == MVT::i64) {
+ if (RetVT == MVT::bf16)
+ return UINTTOFP_I64_BF16;
if (RetVT == MVT::f16)
return UINTTOFP_I64_F16;
if (RetVT == MVT::f32)
diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
index 82359769c7c22..3422ea63e748a 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
@@ -1098,17 +1098,99 @@ define bfloat @fcvt_bf16_wu_load(ptr %p) nounwind {
ret bfloat %1
}
-; TODO: The following tests error on rv32 with zfbfmin enabled.
-
-; define bfloat @fcvt_bf16_l(i64 %a) nounwind {
-; %1 = sitofp i64 %a to bfloat
-; ret bfloat %1
-; }
+define bfloat @fcvt_bf16_l(i64 %a) nounwind {
+; CHECK32ZFBFMIN-LABEL: fcvt_bf16_l:
+; CHECK32ZFBFMIN: # %bb.0:
+; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
+; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32ZFBFMIN-NEXT: call __floatdibf
+; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
+; CHECK32ZFBFMIN-NEXT: ret
+;
+; RV32ID-LABEL: fcvt_bf16_l:
+; RV32ID: # %bb.0:
+; RV32ID-NEXT: addi sp, sp, -16
+; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ID-NEXT: call __floatdisf
+; RV32ID-NEXT: call __truncsfbf2
+; RV32ID-NEXT: fmv.x.w a0, fa0
+; RV32ID-NEXT: lui a1, 1048560
+; RV32ID-NEXT: or a0, a0, a1
+; RV32ID-NEXT: fmv.w.x fa0, a0
+; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ID-NEXT: addi sp, sp, 16
+; RV32ID-NEXT: ret
+;
+; CHECK64ZFBFMIN-LABEL: fcvt_bf16_l:
+; CHECK64ZFBFMIN: # %bb.0:
+; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK64ZFBFMIN-NEXT: ret
+;
+; RV64ID-LABEL: fcvt_bf16_l:
+; RV64ID: # %bb.0:
+; RV64ID-NEXT: addi sp, sp, -16
+; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64ID-NEXT: fcvt.s.l fa0, a0
+; RV64ID-NEXT: call __truncsfbf2
+; RV64ID-NEXT: fmv.x.w a0, fa0
+; RV64ID-NEXT: lui a1, 1048560
+; RV64ID-NEXT: or a0, a0, a1
+; RV64ID-NEXT: fmv.w.x fa0, a0
+; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64ID-NEXT: addi sp, sp, 16
+; RV64ID-NEXT: ret
+ %1 = sitofp i64 %a to bfloat
+ ret bfloat %1
+}
-; define bfloat @fcvt_bf16_lu(i64 %a) nounwind {
-; %1 = uitofp i64 %a to bfloat
-; ret bfloat %1
-; }
+define bfloat @fcvt_bf16_lu(i64 %a) nounwind {
+; CHECK32ZFBFMIN-LABEL: fcvt_bf16_lu:
+; CHECK32ZFBFMIN: # %bb.0:
+; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
+; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32ZFBFMIN-NEXT: call __floatundibf
+; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
+; CHECK32ZFBFMIN-NEXT: ret
+;
+; RV32ID-LABEL: fcvt_bf16_lu:
+; RV32ID: # %bb.0:
+; RV32ID-NEXT: addi sp, sp, -16
+; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ID-NEXT: call __floatundisf
+; RV32ID-NEXT: call __truncsfbf2
+; RV32ID-NEXT: fmv.x.w a0, fa0
+; RV32ID-NEXT: lui a1, 1048560
+; RV32ID-NEXT: or a0, a0, a1
+; RV32ID-NEXT: fmv.w.x fa0, a0
+; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ID-NEXT: addi sp, sp, 16
+; RV32ID-NEXT: ret
+;
+; CHECK64ZFBFMIN-LABEL: fcvt_bf16_lu:
+; CHECK64ZFBFMIN: # %bb.0:
+; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK64ZFBFMIN-NEXT: ret
+;
+; RV64ID-LABEL: fcvt_bf16_lu:
+; RV64ID: # %bb.0:
+; RV64ID-NEXT: addi sp, sp, -16
+; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64ID-NEXT: fcvt.s.lu fa0, a0
+; RV64ID-NEXT: call __truncsfbf2
+; RV64ID-NEXT: fmv.x.w a0, fa0
+; RV64ID-NEXT: lui a1, 1048560
+; RV64ID-NEXT: or a0, a0, a1
+; RV64ID-NEXT: fmv.w.x fa0, a0
+; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64ID-NEXT: addi sp, sp, 16
+; RV64ID-NEXT: ret
+ %1 = uitofp i64 %a to bfloat
+ ret bfloat %1
+}
define bfloat @fcvt_bf16_s(float %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_bf16_s:
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