[llvm] fplower update (PR #128917)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 5 16:57:34 PST 2025
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/128917
>From 68955baef614f782fa71401aef600cc4f897355b Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 5 Mar 2025 19:57:17 -0500
Subject: [PATCH] getregclassfor add t16
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fe095414e5172..b6d1c401507c2 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16965,6 +16965,8 @@ SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)
return Subtarget->isWave64() ? &AMDGPU::SReg_64RegClass
: &AMDGPU::SReg_32RegClass;
+ if (VT == MVT::f16 && TRI->isVGPRClass(RC))
+ return RC;
if (!TRI->isSGPRClass(RC) && !isDivergent)
return TRI->getEquivalentSGPRClass(RC);
if (TRI->isSGPRClass(RC) && isDivergent)
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