[llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)

[Philip Reames via llvm-commits]

preames wrote:

> I don't fully understand this, can you please explain your thought? I also am interested in this.

I'm suggesting that even if we move to using the vmv0 register class into reg alloc (as look suggested), that we probably still want a schedule dag mutation to bias the scheduling of mask producing vs mask consuming instructions.  In theory, the scheduler should do this for us based on register pressure, but having a dag mutation is likely to be more robust.  We might remove it later, or we might not.

https://github.com/llvm/llvm-project/pull/129296