[llvm] dd662d8 - [RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl (#81123)
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Wed Mar 5 04:29:07 PST 2025
Author: Alex Bradbury
Date: 2025-03-05T12:29:04Z
New Revision: dd662d8028de628f569a62887378e4ed48d57fb9
URL: https://github.com/llvm/llvm-project/commit/dd662d8028de628f569a62887378e4ed48d57fb9
DIFF: https://github.com/llvm/llvm-project/commit/dd662d8028de628f569a62887378e4ed48d57fb9.diff
LOG: [RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl (#81123)
Split out from #77610 and features a test, as a buggy version of this
caused a regression when landing that patch (the previous version had a
typo picking the wrong register as the source).
This is also motivated by future changes to MachineCopyPropagation which will use this information to determine if we have been left with a nop mv.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 913169c00b642..7d5f97bf964aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1650,6 +1650,14 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
break;
+ case RISCV::ADD:
+ if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0 &&
+ MI.getOperand(2).isReg())
+ return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
+ if (MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0 &&
+ MI.getOperand(1).isReg())
+ return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ break;
case RISCV::ADDI:
// Operand 1 can be a frameindex but callers expect registers
if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll b/llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
index cf7cef83bcc13..2fcb911c2654a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
@@ -33,13 +33,13 @@ define void @constant_fold_barrier_i128(ptr %p) {
; RV32-NEXT: add a2, a2, a1
; RV32-NEXT: add a6, a3, zero
; RV32-NEXT: sltu a1, a2, a1
-; RV32-NEXT: sltu a3, a6, a3
+; RV32-NEXT: sltu a3, a3, a3
; RV32-NEXT: add a6, a6, a1
; RV32-NEXT: seqz a7, a6
; RV32-NEXT: and a1, a7, a1
; RV32-NEXT: add a7, a4, zero
; RV32-NEXT: add a5, a5, zero
-; RV32-NEXT: sltu a4, a7, a4
+; RV32-NEXT: sltu a4, a4, a4
; RV32-NEXT: or a1, a3, a1
; RV32-NEXT: add a7, a7, a1
; RV32-NEXT: seqz a3, a7
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 820918f811a34..38675a6461b3b 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -135,7 +135,7 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
EXPECT_EQ(MI4Res->Destination->getReg(), RISCV::F1_D);
EXPECT_EQ(MI4Res->Source->getReg(), RISCV::F2_D);
- // ADD. TODO: Should return true for add reg, x0 and add x0, reg.
+ // ADD.
MachineInstr *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X3)
@@ -148,14 +148,18 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
.addReg(RISCV::X2)
.getInstr();
auto MI6Res = TII->isCopyInstrImpl(*MI6);
- EXPECT_FALSE(MI6Res.has_value());
+ ASSERT_TRUE(MI6Res.has_value());
+ EXPECT_EQ(MI6Res->Destination->getReg(), RISCV::X1);
+ EXPECT_EQ(MI6Res->Source->getReg(), RISCV::X2);
MachineInstr *MI7 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X0)
.getInstr();
auto MI7Res = TII->isCopyInstrImpl(*MI7);
- EXPECT_FALSE(MI7Res.has_value());
+ ASSERT_TRUE(MI7Res.has_value());
+ EXPECT_EQ(MI7Res->Destination->getReg(), RISCV::X1);
+ EXPECT_EQ(MI7Res->Source->getReg(), RISCV::X2);
}
TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
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