[llvm] [shrinkwrap] PowerPC's FP register should be honored when processing the save point for prologue. (PR #129855)
Tony Varghese via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 5 01:19:50 PST 2025
https://github.com/tonykuttai created https://github.com/llvm/llvm-project/pull/129855
When generating code for functions that have `__builtin_frame_address` calls and `noinline` attribute, prologue was not emitted correctly leading to an assertion failure in PowerPC. The issue was due to improper insertion of prologue for a function that contain llvm `__builtin_frame_address`.
Shrink-wrap pass computes the save and restore points of a function. Default points are the entry and exit points of the function. During shrink-wrapping the frame-pointer was not honored like the stack pointer and it was considered as a callee-saved register. This change will treat the FP similar to SP and will insert the prolog on top the instruction containing FP.
>From 91b493e0ab9b31ec5bb02ccefc00efd4fae8a829 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 5 Mar 2025 04:05:52 -0500
Subject: [PATCH] PPC's FP register should be honored when processing the save
point for prolog by shrinkwrap pass
---
.../include/llvm/CodeGen/TargetRegisterInfo.h | 7 ++
llvm/lib/CodeGen/ShrinkWrap.cpp | 6 +-
llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 4 +
.../PowerPC/shrink-wrap-frame-pointer.ll | 103 ++++++++++++++++++
4 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 3206cc4518821..b339bcd7fa5fb 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1243,6 +1243,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
return false;
}
+ /// Some targets delay assigning the frame until late and use a placeholder
+ /// to represent it earlier. This method can be used to identify the frame
+ /// register placeholder.
+ virtual bool isVirtualFrameRegister(MCRegister Reg) const {
+ return false;
+ }
+
virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
return {};
}
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index fa57eb30fac43..c723a1aabd552 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -348,10 +348,14 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS,
// calling convention definitions, so we need to watch for it, too. An LR
// mentioned implicitly by a return (or "branch to link register")
// instruction we can ignore, otherwise we may pessimize shrinkwrapping.
+ // PPC's Frame pointer (FP) is also not described as a callee-saved register.
+ // Until the FP is assigned a Physical Register PPC's FP needs to be checked
+ // separately.
UseOrDefCSR =
(!MI.isCall() && PhysReg == SP) ||
RCI.getLastCalleeSavedAlias(PhysReg) ||
- (!MI.isReturn() && TRI->isNonallocatableRegisterCalleeSave(PhysReg));
+ (!MI.isReturn() && TRI->isNonallocatableRegisterCalleeSave(PhysReg)) ||
+ (!MI.isReturn() && TRI->isVirtualFrameRegister(PhysReg));
} else if (MO.isRegMask()) {
// Check if this regmask clobbers any of the CSRs.
for (unsigned Reg : getCurrentCSRs(RS)) {
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 274c7cb68ae0a..103059d0e29ab 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -176,6 +176,10 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override {
return Reg == PPC::LR || Reg == PPC::LR8;
}
+
+ bool isVirtualFrameRegister(MCRegister Reg) const override {
+ return Reg == PPC::FP || Reg == PPC::FP8;
+ }
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll b/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
new file mode 100644
index 0000000000000..df76cf965b51b
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
@@ -0,0 +1,103 @@
+; Test file to check shrink-wrap pass
+
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC32-AIX
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC64-AIX
+
+ at .str = private unnamed_addr constant [50 x i8] c"parent_frame_pointer > __builtin_frame_address(0)\00", align 1
+ at .str.1 = private unnamed_addr constant [8 x i8] c"bad.cpp\00", align 1
+
+; Function Attrs: mustprogress noinline nounwind
+define void @_Z3fooPv(ptr noundef readnone %parent_frame_pointer) local_unnamed_addr #0 {
+
+; POWERPC32-AIX-LABEL: ._Z3fooPv:
+; POWERPC32-AIX: # %bb.0:
+; POWERPC32-AIX-NEXT: mflr 0
+; POWERPC32-AIX-NEXT: stwu 1, -64(1)
+; POWERPC32-AIX-NEXT: cmplw 3, 1
+; POWERPC32-AIX-NEXT: stw 0, 72(1)
+; POWERPC32-AIX-NEXT: ble- 0, L..BB0_2
+; POWERPC32-AIX-NEXT: # %bb.1:
+; POWERPC32-AIX-NEXT: addi 1, 1, 64
+; POWERPC32-AIX-NEXT: lwz 0, 8(1)
+; POWERPC32-AIX-NEXT: mtlr 0
+; POWERPC32-AIX-NEXT: blr
+; POWERPC32-AIX-NEXT: L..BB0_2:
+; POWERPC32-AIX-NEXT: lwz 4, L..C0(2)
+; POWERPC32-AIX-NEXT: li 5, 6
+; POWERPC32-AIX-NEXT: addi 3, 4, 8
+; POWERPC32-AIX-NEXT: bl .__assert[PR]
+; POWERPC32-AIX-NEXT: nop
+
+; POWERPC64-AIX-LABEL: ._Z3fooPv:
+; POWERPC64-AIX: # %bb.0:
+; POWERPC64-AIX-NEXT: mflr 0
+; POWERPC64-AIX-NEXT: stdu 1, -112(1)
+; POWERPC64-AIX-NEXT: cmpld 3, 1
+; POWERPC64-AIX-NEXT: std 0, 128(1)
+; POWERPC64-AIX-NEXT: ble- 0, L..BB0_2
+; POWERPC64-AIX-NEXT: # %bb.1:
+; POWERPC64-AIX-NEXT: addi 1, 1, 112
+; POWERPC64-AIX-NEXT: ld 0, 16(1)
+; POWERPC64-AIX-NEXT: mtlr 0
+; POWERPC64-AIX-NEXT: blr
+; POWERPC64-AIX-NEXT: L..BB0_2:
+; POWERPC64-AIX-NEXT: ld 4, L..C0(2)
+; POWERPC64-AIX-NEXT: li 5, 6
+; POWERPC64-AIX-NEXT: addi 3, 4, 8
+; POWERPC64-AIX-NEXT: bl .__assert[PR]
+; POWERPC64-AIX-NEXT: nop
+
+entry:
+ %0 = tail call ptr @llvm.frameaddress.p0(i32 0)
+ %cmp = icmp ugt ptr %parent_frame_pointer, %0
+ br i1 %cmp, label %cond.end, label %cond.false
+
+cond.false: ; preds = %entry
+ tail call void @__assert(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 6) #4
+ unreachable
+
+cond.end: ; preds = %entry
+ ret void
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare ptr @llvm.frameaddress.p0(i32 immarg) #1
+
+; Function Attrs: noreturn nounwind
+declare void @__assert(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2
+
+; Function Attrs: mustprogress norecurse nounwind
+define noundef i32 @main() local_unnamed_addr #3 {
+; POWERPC32-AIX-LABEL: .main:
+; POWERPC32-AIX: # %bb.0:
+; POWERPC32-AIX-NEXT: mflr 0
+; POWERPC32-AIX-NEXT: stwu 1, -64(1)
+; POWERPC32-AIX-NEXT: mr 3, 1
+; POWERPC32-AIX-NEXT: stw 0, 72(1)
+; POWERPC32-AIX-NEXT: bl ._Z3fooPv
+; POWERPC32-AIX-NEXT: nop
+; POWERPC32-AIX-NEXT: li 3, 0
+; POWERPC32-AIX-NEXT: addi 1, 1, 64
+; POWERPC32-AIX-NEXT: lwz 0, 8(1)
+; POWERPC32-AIX-NEXT: mtlr 0
+; POWERPC32-AIX-NEXT: blr
+
+; POWERPC64-AIX-LABEL: .main:
+; POWERPC64-AIX: # %bb.0:
+; POWERPC64-AIX-NEXT: mflr 0
+; POWERPC64-AIX-NEXT: stdu 1, -112(1)
+; POWERPC64-AIX-NEXT: mr 3, 1
+; POWERPC64-AIX-NEXT: std 0, 128(1)
+; POWERPC64-AIX-NEXT: bl ._Z3fooPv
+; POWERPC64-AIX-NEXT: nop
+; POWERPC64-AIX-NEXT: li 3, 0
+; POWERPC64-AIX-NEXT: addi 1, 1, 112
+; POWERPC64-AIX-NEXT: ld 0, 16(1)
+; POWERPC64-AIX-NEXT: mtlr 0
+; POWERPC64-AIX-NEXT: blr
+
+entry:
+ %0 = tail call ptr @llvm.frameaddress.p0(i32 0)
+ tail call void @_Z3fooPv(ptr noundef %0)
+ ret i32 0
+}
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