[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[via llvm-commits]

================
@@ -35,6 +35,48 @@ static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
       .addImm(Value.getZExtValue());
 }
 
+static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the ZPR Register");
+  // For ZPR, we typically use DUPM instruction to load immediate values
+  return MCInstBuilder(AArch64::DUPM_ZI)
+      .addReg(Reg)
+      .addImm(Value.getZExtValue());
+}
+
+static MCInst loadPPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the PPR Register");
+  // For PPR, we typically use PTRUE instruction to set predicate registers
+  return MCInstBuilder(AArch64::PTRUE_B)
+      .addReg(Reg)
+      .addImm(31); // All lanes true
+}
+
+// Generates instruction to load an FP immediate value into a register.
+static unsigned getLoadFPImmediateOpcode(unsigned RegBitWidth) {
+  switch (RegBitWidth) {
+  case 64:
+    return AArch64::FMOVDi; 
+  case 128:
+    return AArch64::MOVIv2d_ns;
+  }
+  llvm_unreachable("Invalid Value Width");
+}
+
+
+// Generates instruction to load an FP immediate value into a register.
+static MCInst loadFPImmediate(MCRegister Reg, unsigned RegBitWidth,
+                            const APInt &Value) {
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the FP Register");
+  return MCInstBuilder(getLoadFPImmediateOpcode(RegBitWidth))
----------------
lakshayk-nv wrote:

> ADDXrr is a psuedo, so I wouldn't expect it to work (unless it was expanded?). The test should probably be testing ADDXri, ADDXrs and ADDXrx, as those are the real instructions. It means that the tests have never worked on AArch64 with llvm-exegesis enabled, which would be good to fix just for the sake of having clean tests.
>
>>
`ADDXri, ADDXrs, ADDXrx` currently throws "Not all operands were initialized by the snippet generator" error.
We are planning to fix them in coming patches. Currently we started with some low hanging fruites, thus picked this opocdes which were throwing warnings and easy to fix, but yes our plan is to fix as much as we can for all the opcodes for aarch64.

- ADDV's variants which requires setting register class of FPR64 and FPR128; 
- FADDV_VPZ's variants which requires PPR and ZPR(128 bit width) register class.

https://github.com/llvm/llvm-project/pull/127564