[llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

> As an aside, I suspect we're still going to want some kind of scheduling false dependency even on the register class representation. Expecting the scheduler to perfectly handle register pressure on size=1 register classes seems like a big ask. I'd suggest starting with the scheduling dependency in place (over the new representation), and then remove it in a separate change.

I don't fully understand this, can you please explain your thought? I also am interested in this.

https://github.com/llvm/llvm-project/pull/129296