[llvm] 5cc033b - [AMDGPU][True16][CodeGen] fshr true16 pattern (#129085)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 4 12:43:46 PST 2025
Author: Brox Chen
Date: 2025-03-04T15:43:43-05:00
New Revision: 5cc033b5f2ac0f257ee6c7fd457da0425dc64d37
URL: https://github.com/llvm/llvm-project/commit/5cc033b5f2ac0f257ee6c7fd457da0425dc64d37
DIFF: https://github.com/llvm/llvm-project/commit/5cc033b5f2ac0f257ee6c7fd457da0425dc64d37.diff
LOG: [AMDGPU][True16][CodeGen] fshr true16 pattern (#129085)
true16 pattern for fshr.
GlobalIsel will be enabled latter when merge_value selection is
supported in true16 mode
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/test/CodeGen/AMDGPU/bswap.ll
llvm/test/CodeGen/AMDGPU/fshr.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e8daa4b542e02..63f66023837a2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2511,6 +2511,33 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
} // end True16Predicate = NotHasTrue16BitInsts
+let True16Predicate = UseRealTrue16Insts in {
+def : GCNPat <
+ (rotr i32:$src0, i32:$src1),
+ (V_ALIGNBIT_B32_t16_e64 /* src0_modifiers */ 0, $src0,
+ /* src1_modifiers */ 0, $src0,
+ /* src2_modifiers */ 0,
+ (EXTRACT_SUBREG $src1, lo16),
+ /* clamp */ 0, /* op_sel */ 0)
+>;
+
+def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
+ (V_ALIGNBIT_B32_t16_e64 0, /* src0_modifiers */
+ (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
+ 0, /* src1_modifiers */
+ (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
+ 0, /* src2_modifiers */
+ (i16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)),
+ /* clamp */ 0, /* op_sel */ 0)>;
+
+def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
+ (V_ALIGNBIT_B32_t16_e64 /* src0_modifiers */ 0, $src0,
+ /* src1_modifiers */ 0, $src1,
+ /* src2_modifiers */ 0,
+ (EXTRACT_SUBREG VGPR_32:$src2, lo16),
+ /* clamp */ 0, /* op_sel */ 0)>;
+} // end True16Predicate = UseRealTrue16Insts
+
let True16Predicate = UseFakeTrue16Insts in {
def : GCNPat <
(rotr i32:$src0, i32:$src1),
diff --git a/llvm/test/CodeGen/AMDGPU/bswap.ll b/llvm/test/CodeGen/AMDGPU/bswap.ll
index b98ca1ff55f59..a95a1aba0c914 100644
--- a/llvm/test/CodeGen/AMDGPU/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/bswap.ll
@@ -737,25 +737,15 @@ define i64 @v_bswap_i48(i64 %src) {
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-REAL16-LABEL: v_bswap_i48:
-; GFX11-REAL16: ; %bb.0:
-; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-REAL16-NEXT: v_perm_b32 v2, 0, v0, 0x10203
-; GFX11-REAL16-NEXT: v_perm_b32 v1, 0, v1, 0x10203
-; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-REAL16-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
-; GFX11-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-REAL16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: v_bswap_i48:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, 0, v0, 0x10203
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, 0, v1, 0x10203
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_bswap_i48:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_perm_b32 v2, 0, v0, 0x10203
+; GFX11-NEXT: v_perm_b32 v0, 0, v1, 0x10203
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-NEXT: v_alignbit_b32 v0, v2, v0, 16
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc i64 %src to i48
%bswap = call i48 @llvm.bswap.i48(i48 %trunc)
%zext = zext i48 %bswap to i64
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index 5ca81ce9f9e07..c3d82e38d1985 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -4,7 +4,10 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX89,GFX9
; RUN: llc < %s -mtriple=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefix=R600
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX10
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX11
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX12,GFX12-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX12,GFX12-FAKE16
declare i32 @llvm.fshr.i32(i32, i32, i32)
declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
@@ -81,17 +84,55 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX10-NEXT: global_store_dword v1, v0, s[6:7]
; GFX10-NEXT: s_endpgm
;
-; GFX11-LABEL: fshr_i32:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, v0
-; GFX11-NEXT: global_store_b32 v1, v0, s[4:5]
-; GFX11-NEXT: s_endpgm
+; GFX11-TRUE16-LABEL: fshr_i32:
+; GFX11-TRUE16: ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
+; GFX11-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX11-TRUE16-NEXT: s_endpgm
+;
+; GFX11-FAKE16-LABEL: fshr_i32:
+; GFX11-FAKE16: ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, v0
+; GFX11-FAKE16-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX11-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: fshr_i32:
+; GFX12-TRUE16: ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT: s_clause 0x1
+; GFX12-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
+; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
+; GFX12-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: fshr_i32:
+; GFX12-FAKE16: ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT: s_clause 0x1
+; GFX12-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
+; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, v0
+; GFX12-FAKE16-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
store i32 %0, ptr addrspace(1) %in
@@ -162,6 +203,15 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX11-NEXT: v_alignbit_b32 v1, s2, s3, 7
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_i32_imm:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_alignbit_b32 v1, s2, s3, 7
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
store i32 %0, ptr addrspace(1) %in
@@ -248,20 +298,67 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX10-NEXT: global_store_dwordx2 v3, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm
;
-; GFX11-LABEL: fshr_v2i32:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_clause 0x2
-; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s7
-; GFX11-NEXT: v_mov_b32_e32 v2, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_alignbit_b32 v1, s1, s3, v0
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s2, v2
-; GFX11-NEXT: global_store_b64 v3, v[0:1], s[4:5]
-; GFX11-NEXT: s_endpgm
+; GFX11-TRUE16-LABEL: fshr_v2i32:
+; GFX11-TRUE16: ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT: s_clause 0x2
+; GFX11-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
+; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, v0.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, v0.h
+; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-TRUE16-NEXT: s_endpgm
+;
+; GFX11-FAKE16-LABEL: fshr_v2i32:
+; GFX11-FAKE16: ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT: s_clause 0x2
+; GFX11-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
+; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s7
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, s1, s3, v0
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s2, v2
+; GFX11-FAKE16-NEXT: global_store_b64 v3, v[0:1], s[4:5]
+; GFX11-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: fshr_v2i32:
+; GFX12-TRUE16: ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT: s_clause 0x2
+; GFX12-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
+; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s6
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, v0.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, v0.h
+; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: fshr_v2i32:
+; GFX12-FAKE16: ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT: s_clause 0x2
+; GFX12-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
+; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s7
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, s1, s3, v0
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, s0, s2, v2
+; GFX12-FAKE16-NEXT: global_store_b64 v3, v[0:1], s[4:5]
+; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
store <2 x i32> %0, ptr addrspace(1) %in
@@ -347,6 +444,18 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX11-NEXT: v_alignbit_b32 v0, s0, s2, 7
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v2i32_imm:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_alignbit_b32 v1, s1, s3, 9
+; GFX12-NEXT: v_alignbit_b32 v0, s0, s2, 7
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
store <2 x i32> %0, ptr addrspace(1) %in
@@ -459,24 +568,85 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm
;
-; GFX11-LABEL: fshr_v4i32:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_clause 0x2
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
-; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v6, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
-; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_alignbit_b32 v3, s11, s15, v0
-; GFX11-NEXT: v_alignbit_b32 v2, s10, s14, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_alignbit_b32 v1, s9, s13, v4
-; GFX11-NEXT: v_alignbit_b32 v0, s8, s12, v5
-; GFX11-NEXT: global_store_b128 v6, v[0:3], s[4:5]
-; GFX11-NEXT: s_endpgm
+; GFX11-TRUE16-LABEL: fshr_v4i32:
+; GFX11-TRUE16: ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT: s_clause 0x2
+; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
+; GFX11-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, v0.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, v1.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, v4.l
+; GFX11-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[4:5]
+; GFX11-TRUE16-NEXT: s_endpgm
+;
+; GFX11-FAKE16-LABEL: fshr_v4i32:
+; GFX11-FAKE16: ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT: s_clause 0x2
+; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
+; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, 0
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v3, s11, s15, v0
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v2, s10, s14, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, s9, s13, v4
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s8, s12, v5
+; GFX11-FAKE16-NEXT: global_store_b128 v6, v[0:3], s[4:5]
+; GFX11-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: fshr_v4i32:
+; GFX12-TRUE16: ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT: s_clause 0x2
+; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
+; GFX12-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, s0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, v0.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, v0.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, v1.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, v4.l
+; GFX12-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[4:5]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: fshr_v4i32:
+; GFX12-FAKE16: ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT: s_clause 0x2
+; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
+; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, 0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v3, s11, s15, v0
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v2, s10, s14, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, s9, s13, v4
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, s8, s12, v5
+; GFX12-FAKE16-NEXT: global_store_b128 v6, v[0:3], s[4:5]
+; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
store <4 x i32> %0, ptr addrspace(1) %in
@@ -580,6 +750,20 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX11-NEXT: v_alignbit_b32 v0, s8, s12, 1
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v4i32_imm:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_alignbit_b32 v3, s11, s15, 1
+; GFX12-NEXT: v_alignbit_b32 v2, s10, s14, 9
+; GFX12-NEXT: v_alignbit_b32 v1, s9, s13, 7
+; GFX12-NEXT: v_alignbit_b32 v0, s8, s12, 1
+; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
store <4 x i32> %0, ptr addrspace(1) %in
@@ -604,11 +788,37 @@ define i32 @v_fshr_i32(i32 %src0, i32 %src1, i32 %src2) {
; GFX10-NEXT: v_alignbit_b32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_i32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, v2
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_i32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_i32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v1, v2
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_i32:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_i32:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v1, v2
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call i32 @llvm.fshr.i32(i32 %src0, i32 %src1, i32 %src2)
ret i32 %ret
}
@@ -633,12 +843,41 @@ define <2 x i32> @v_fshr_v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v2i32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v2, v4
-; GFX11-NEXT: v_alignbit_b32 v1, v1, v3, v5
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v2i32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v2i32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, v1, v3, v5
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v2i32:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v2i32:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, v1, v3, v5
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2)
ret <2 x i32> %ret
}
@@ -665,13 +904,45 @@ define <3 x i32> @v_fshr_v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2
; GFX10-NEXT: v_alignbit_b32 v2, v2, v5, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v3i32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v3, v6
-; GFX11-NEXT: v_alignbit_b32 v1, v1, v4, v7
-; GFX11-NEXT: v_alignbit_b32 v2, v2, v5, v8
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v3i32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v3, v6.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v4, v7.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v2, v5, v8.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v3i32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v3, v6
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, v1, v4, v7
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v2, v2, v5, v8
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v3i32:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v3, v6.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, v1, v4, v7.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v2, v2, v5, v8.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v3i32:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v3, v6
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, v1, v4, v7
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v2, v2, v5, v8
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <3 x i32> @llvm.fshr.v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2)
ret <3 x i32> %ret
}
@@ -700,14 +971,49 @@ define <4 x i32> @v_fshr_v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2
; GFX10-NEXT: v_alignbit_b32 v3, v3, v7, v11
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v4i32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v4, v8
-; GFX11-NEXT: v_alignbit_b32 v1, v1, v5, v9
-; GFX11-NEXT: v_alignbit_b32 v2, v2, v6, v10
-; GFX11-NEXT: v_alignbit_b32 v3, v3, v7, v11
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v4i32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v4, v8.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v5, v9.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v2, v6, v10.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, v3, v7, v11.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v4i32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v4, v8
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, v1, v5, v9
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v2, v2, v6, v10
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v3, v3, v7, v11
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v4i32:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v4, v8.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, v1, v5, v9.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v2, v2, v6, v10.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v3, v3, v7, v11.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v4i32:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v4, v8
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, v1, v5, v9
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v2, v2, v6, v10
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v3, v3, v7, v11
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2)
ret <4 x i32> %ret
}
@@ -756,16 +1062,61 @@ define i16 @v_fshr_i16(i16 %src0, i16 %src1, i16 %src2) {
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX11-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX11-NEXT: v_lshrrev_b16 v1, v2, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b16 v0, v3, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_xor_b16 v2.l, v0.h, -1
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v1, v2, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_i16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_xor_b16 v2.l, v0.h, -1
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.h, v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_i16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v1, v2, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v0, v3, v0
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call i16 @llvm.fshr.i16(i16 %src0, i16 %src1, i16 %src2)
ret i16 %ret
}
@@ -846,6 +1197,24 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2
; GFX11-NEXT: v_pk_lshlrev_b16 v0, v3, v0
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fshr_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX12-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX12-NEXT: v_and_b32_e32 v2, 0xf000f, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_and_b32_e32 v3, 0xf000f, v3
+; GFX12-NEXT: v_pk_lshrrev_b16 v1, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_pk_lshlrev_b16 v0, v3, v0
+; GFX12-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%ret = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2)
ret <2 x i16> %ret
}
@@ -946,32 +1315,117 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v3i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX11-NEXT: v_xor_b32_e32 v10, -1, v4
-; GFX11-NEXT: v_lshlrev_b16 v6, 1, v6
-; GFX11-NEXT: v_xor_b32_e32 v9, -1, v7
-; GFX11-NEXT: v_lshlrev_b16 v1, 1, v1
-; GFX11-NEXT: v_lshrrev_b16 v7, v7, v8
-; GFX11-NEXT: v_lshlrev_b16 v0, v10, v0
-; GFX11-NEXT: v_lshrrev_b16 v2, v4, v2
-; GFX11-NEXT: v_lshlrev_b16 v6, v9, v6
-; GFX11-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX11-NEXT: v_lshrrev_b16 v3, v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b16 v1, v4, v1
-; GFX11-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v2.h, v5.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v6.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v1.h, v7.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v3.h, v4.l, -1
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v4.h, v7.l, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v2.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, v4.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v3.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, v5.l, v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v10, -1, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 1, v6
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v9, -1, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v7, v7, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v10, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, -1, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v3, v5, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v3i16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v2.h, v5.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v6.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v1.h, v7.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v3.h, v4.l, -1
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v4.h, v7.l, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, v2.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, v1.h, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v1.h, v4.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v3.h, v0.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.l, v5.l, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v3i16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v10, -1, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v6, 1, v6
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v9, -1, v7
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v7, v7, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v0, v10, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v2, v4, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v6, v9, v6
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v4, -1, v5
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v3, v5, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, v4, v1
+; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2)
ret <3 x i16> %ret
}
@@ -1099,40 +1553,147 @@ define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2
; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v4i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_lshrrev_b16 v6, v7, v6
-; GFX11-NEXT: v_lshlrev_b16 v8, 1, v8
-; GFX11-NEXT: v_xor_b32_e32 v7, -1, v7
-; GFX11-NEXT: v_lshlrev_b16 v9, 1, v9
-; GFX11-NEXT: v_xor_b32_e32 v12, -1, v10
-; GFX11-NEXT: v_lshlrev_b16 v1, 1, v1
-; GFX11-NEXT: v_xor_b32_e32 v13, -1, v5
-; GFX11-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX11-NEXT: v_xor_b32_e32 v14, -1, v4
-; GFX11-NEXT: v_lshlrev_b16 v7, v7, v8
-; GFX11-NEXT: v_lshrrev_b16 v8, v10, v11
-; GFX11-NEXT: v_lshlrev_b16 v9, v12, v9
-; GFX11-NEXT: v_lshlrev_b16 v1, v13, v1
-; GFX11-NEXT: v_lshlrev_b16 v0, v14, v0
-; GFX11-NEXT: v_lshrrev_b16 v2, v4, v2
-; GFX11-NEXT: v_lshrrev_b16 v3, v5, v3
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v6
-; GFX11-NEXT: v_or_b32_e32 v5, v9, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v4i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v7.l, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v8.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v3.h, v7.l, -1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 1, v9.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v4.h, v10.l, -1
+; GFX11-TRUE16-NEXT: v_xor_b16 v5.h, v5.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v6.l, v4.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.h, v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, v4.h, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v5.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v6.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.l, v5.l, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v3.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v4i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 1, v8
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v9
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v12, -1, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v13, -1, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v14, -1, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, v7, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v8, v10, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, v13, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v14, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v4i16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.h, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v8.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v3.h, v7.l, -1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.h, 1, v9.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v4.h, v10.l, -1
+; GFX12-TRUE16-NEXT: v_xor_b16 v5.h, v5.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v6.l, v4.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, v3.h, v1.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v3.h, v10.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.h, v4.h, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, v5.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v6.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.l, v4.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v3.l, v5.l, v3.l
+; GFX12-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v0.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v3.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v3.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v4i16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v6, v7, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v8, 1, v8
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v7
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v9
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v12, -1, v10
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v13, -1, v5
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v14, -1, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v7, v7, v8
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v8, v10, v11
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v9, v12, v9
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, v13, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v0, v14, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v2, v4, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b16 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v9, v8
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2)
ret <4 x i16> %ret
}
@@ -1199,6 +1760,23 @@ define i64 @v_fshr_i64(i64 %src0, i64 %src1, i64 %src2) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fshr_i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 1, v[0:1]
+; GFX12-NEXT: v_not_b32_e32 v5, v4
+; GFX12-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], v5, v[0:1]
+; GFX12-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%ret = call i64 @llvm.fshr.i64(i64 %src0, i64 %src1, i64 %src2)
ret i64 %ret
}
@@ -1296,6 +1874,30 @@ define <2 x i64> @v_fshr_v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fshr_v2i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 1, v[0:1]
+; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 1, v[2:3]
+; GFX12-NEXT: v_not_b32_e32 v9, v8
+; GFX12-NEXT: v_not_b32_e32 v11, v10
+; GFX12-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
+; GFX12-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], v9, v[0:1]
+; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], v11, v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX12-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX12-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%ret = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2)
ret <2 x i64> %ret
}
@@ -1357,20 +1959,73 @@ define i24 @v_fshr_i24(i24 %src0, i24 %src1, i24 %src2) {
; GFX10-NEXT: v_alignbit_b32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v3, 0xaaaaaab, v3
-; GFX11-NEXT: v_mul_u32_u24_e32 v3, 24, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, v2, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 8, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, v2
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_i24:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v3, 0xaaaaaab, v3
+; GFX11-TRUE16-NEXT: v_mul_u32_u24_e32 v3, 24, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 8, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_i24:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v3, 0xaaaaaab, v3
+; GFX11-FAKE16-NEXT: v_mul_u32_u24_e32 v3, 24, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 8, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v1, v2
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_i24:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffffff, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mul_hi_u32 v3, 0xaaaaaab, v3
+; GFX12-TRUE16-NEXT: v_mul_u32_u24_e32 v3, 24, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_sub_nc_u32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v2, 8, v2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_i24:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffffff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_mul_hi_u32 v3, 0xaaaaaab, v3
+; GFX12-FAKE16-NEXT: v_mul_u32_u24_e32 v3, 24, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_sub_nc_u32_e32 v2, v2, v3
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v2, 8, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v1, v2
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call i24 @llvm.fshr.i24(i24 %src0, i24 %src1, i24 %src2)
ret i24 %ret
}
@@ -1460,29 +2115,109 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v2i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6
-; GFX11-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_u32_u24_e32 v6, 24, v6
-; GFX11-NEXT: v_mul_u32_u24_e32 v7, 24, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v6
-; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 8, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 8, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v2, v4
-; GFX11-NEXT: v_alignbit_b32 v1, v1, v3, v5
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v2i24:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffffff, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX11-TRUE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v2i24:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffffff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX11-FAKE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, v1, v3, v5
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v2i24:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffffff, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6
+; GFX12-TRUE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX12-TRUE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX12-TRUE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v2i24:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffffff, v5
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6
+; GFX12-FAKE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX12-FAKE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX12-FAKE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, v1, v3, v5
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2)
ret <2 x i24> %ret
}
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