[llvm] 0f869cc - [SystemZ] Make I5 operand of R[INOX]SGB(Z)? optional (#129512)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 4 09:53:39 PST 2025
Author: Dominik Steenken
Date: 2025-03-04T18:53:36+01:00
New Revision: 0f869cc336a8155da7b095d0ca704dc8b6777092
URL: https://github.com/llvm/llvm-project/commit/0f869cc336a8155da7b095d0ca704dc8b6777092
DIFF: https://github.com/llvm/llvm-project/commit/0f869cc336a8155da7b095d0ca704dc8b6777092.diff
LOG: [SystemZ] Make I5 operand of R[INOX]SGB(Z)? optional (#129512)
The I5 operand of the instructions in RIE-f format is optional and
assumed 0 when not specified. This was not properly modeled thus far,
and is corrected with this PR. In addition, assembly and disassembly
tests are updated to reflect these changes
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/test/MC/Disassembler/SystemZ/insns.txt
llvm/test/MC/SystemZ/insn-good.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index e16f3ed5f9fbc..3e9a515bf1153 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -5210,14 +5210,18 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
}
}
-class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
- RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0>
- : InstRIEf<opcode, (outs cls1:$R1),
+multiclass RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+ RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0> {
+ let Constraints = "$R1 = $R1src", DisableEncoding = "$R1src" in {
+ def "" : InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
imm32zx8:$I5),
- mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> {
- let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
+ mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or>;
+ let I5 = 0 in
+ def Opt : InstRIEf<opcode, (outs cls1:$R1),
+ (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4),
+ mnemonic#"\t$R1, $R2, $I3, $I4", [], I3Or, I4Or>;
+ }
}
class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
@@ -5609,11 +5613,14 @@ class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
}
// An alias of a RotateSelectRIEf, but with
diff erent register sizes.
-class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
- : Alias<6, (outs cls1:$R1),
- (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
- imm32zx8:$I5), []> {
- let Constraints = "$R1 = $R1src";
+multiclass RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2> {
+ let Constraints = "$R1 = $R1src" in {
+ def "" : Alias<6, (outs cls1:$R1),
+ (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
+ imm32zx8:$I5), []>;
+ def Opt : Alias<6, (outs cls1:$R1),
+ (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4), []>;
+ }
}
class MemsetPseudo<DAGOperand lenop, DAGOperand byteop>
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 5b4a79395ca65..2acb4b0339d32 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1556,38 +1556,38 @@ def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
// end bits (operands 2 and 3) are in the range [32, 64).
let Defs = [CC] in {
let isCodeGenOnly = 1 in
- def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
+ defm RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
let CCValues = 0xE, CompareZeroCCMask = 0xE in {
- def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
- def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;
+ defm RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
+ defm RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;
}
}
// On zEC12 we have a variant of RISBG that does not set CC.
let Predicates = [FeatureMiscellaneousExtensions] in {
- def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
- def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;
+ defm RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
+ defm RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;
}
// Forms of RISBG that only affect one word of the destination register.
// They do not set CC.
let Predicates = [FeatureHighWord] in {
- def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
- def RISBLL : RotateSelectAliasRIEf<GR32, GR32>;
- def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>;
- def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>;
- def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>;
- def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
- def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
+ def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
+ defm RISBLL : RotateSelectAliasRIEf<GR32, GR32>;
+ defm RISBLH : RotateSelectAliasRIEf<GR32, GRH32>;
+ defm RISBHL : RotateSelectAliasRIEf<GRH32, GR32>;
+ defm RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>;
+ defm RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
+ defm RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
}
// Rotate second operand left and perform a logical operation with selected
// bits of the first operand. The CC result only describes the selected bits,
// so isn't useful for a full comparison against zero.
let Defs = [CC] in {
- def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
- def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
- def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ defm RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
+ defm ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
+ defm RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index 094b481b81f83..5f15348654c75 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -506,13 +506,13 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?(Opt)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index b9376d422ded2..336bbe2483340 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -516,13 +516,13 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?(Opt)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 5e28bf935a24b..5f2a04c298a25 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -531,13 +531,13 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?(Opt)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index 2c01691707cc3..f68c0d2669ea9 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -531,13 +531,13 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?(Opt)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index f41a7057bb1f6..f8397921bf684 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -469,13 +469,13 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?(Opt)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index 8f0a10d2863a3..039c8146618fe 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -480,13 +480,13 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?(Opt)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index a4e4a2203a467..689d046155a99 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -13968,22 +13968,22 @@
# CHECK: rchp
0xb2 0x3b 0x00 0x00
-# CHECK: risbg %r0, %r0, 0, 0, 0
+# CHECK: risbg %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x55
# CHECK: risbg %r0, %r0, 0, 0, 255
0xec 0x00 0x00 0x00 0xff 0x55
-# CHECK: risbg %r0, %r0, 0, 127, 0
+# CHECK: risbg %r0, %r0, 0, 127
0xec 0x00 0x00 0x7f 0x00 0x55
-# CHECK: risbg %r0, %r0, 255, 0, 0
+# CHECK: risbg %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x55
-# CHECK: risbg %r0, %r15, 0, 0, 0
+# CHECK: risbg %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x55
-# CHECK: risbg %r15, %r0, 0, 0, 0
+# CHECK: risbg %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x55
# CHECK: risbg %r4, %r5, 6, 7, 8
@@ -13992,22 +13992,22 @@
# CHECK: risbgz %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x87 0x08 0x55
-# CHECK: risbgn %r0, %r0, 0, 0, 0
+# CHECK: risbgn %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x59
# CHECK: risbgn %r0, %r0, 0, 0, 255
0xec 0x00 0x00 0x00 0xff 0x59
-# CHECK: risbgn %r0, %r0, 0, 127, 0
+# CHECK: risbgn %r0, %r0, 0, 127
0xec 0x00 0x00 0x7f 0x00 0x59
-# CHECK: risbgn %r0, %r0, 255, 0, 0
+# CHECK: risbgn %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x59
-# CHECK: risbgn %r0, %r15, 0, 0, 0
+# CHECK: risbgn %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x59
-# CHECK: risbgn %r15, %r0, 0, 0, 0
+# CHECK: risbgn %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x59
# CHECK: risbgn %r4, %r5, 6, 7, 8
@@ -14016,43 +14016,43 @@
# CHECK: risbgnz %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x87 0x08 0x59
-# CHECK: risbhg %r0, %r0, 0, 0, 0
+# CHECK: risbhg %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x5d
# CHECK: risbhg %r0, %r0, 0, 0, 63
0xec 0x00 0x00 0x00 0x3f 0x5d
-# CHECK: risbhg %r0, %r0, 0, 255, 0
+# CHECK: risbhg %r0, %r0, 0, 255
0xec 0x00 0x00 0xff 0x00 0x5d
-# CHECK: risbhg %r0, %r0, 255, 0, 0
+# CHECK: risbhg %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x5d
-# CHECK: risbhg %r0, %r15, 0, 0, 0
+# CHECK: risbhg %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x5d
-# CHECK: risbhg %r15, %r0, 0, 0, 0
+# CHECK: risbhg %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x5d
# CHECK: risbhg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x5d
-# CHECK: risblg %r0, %r0, 0, 0, 0
+# CHECK: risblg %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x51
# CHECK: risblg %r0, %r0, 0, 0, 63
0xec 0x00 0x00 0x00 0x3f 0x51
-# CHECK: risblg %r0, %r0, 0, 255, 0
+# CHECK: risblg %r0, %r0, 0, 255
0xec 0x00 0x00 0xff 0x00 0x51
-# CHECK: risblg %r0, %r0, 255, 0, 0
+# CHECK: risblg %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x51
-# CHECK: risblg %r0, %r15, 0, 0, 0
+# CHECK: risblg %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x51
-# CHECK: risblg %r15, %r0, 0, 0, 0
+# CHECK: risblg %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x51
# CHECK: risblg %r4, %r5, 6, 7, 8
@@ -14130,43 +14130,43 @@
# CHECK: rllg %r0, %r0, 524287(%r15)
0xeb 0x00 0xff 0xff 0x7f 0x1c
-# CHECK: rnsbg %r0, %r0, 0, 0, 0
+# CHECK: rnsbg %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x54
# CHECK: rnsbg %r0, %r0, 0, 0, 63
0xec 0x00 0x00 0x00 0x3f 0x54
-# CHECK: rnsbg %r0, %r0, 0, 255, 0
+# CHECK: rnsbg %r0, %r0, 0, 255
0xec 0x00 0x00 0xff 0x00 0x54
-# CHECK: rnsbg %r0, %r0, 255, 0, 0
+# CHECK: rnsbg %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x54
-# CHECK: rnsbg %r0, %r15, 0, 0, 0
+# CHECK: rnsbg %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x54
-# CHECK: rnsbg %r15, %r0, 0, 0, 0
+# CHECK: rnsbg %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x54
# CHECK: rnsbg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x54
-# CHECK: rosbg %r0, %r0, 0, 0, 0
+# CHECK: rosbg %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x56
# CHECK: rosbg %r0, %r0, 0, 0, 63
0xec 0x00 0x00 0x00 0x3f 0x56
-# CHECK: rosbg %r0, %r0, 0, 255, 0
+# CHECK: rosbg %r0, %r0, 0, 255
0xec 0x00 0x00 0xff 0x00 0x56
-# CHECK: rosbg %r0, %r0, 255, 0, 0
+# CHECK: rosbg %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x56
-# CHECK: rosbg %r0, %r15, 0, 0, 0
+# CHECK: rosbg %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x56
-# CHECK: rosbg %r15, %r0, 0, 0, 0
+# CHECK: rosbg %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x56
# CHECK: rosbg %r4, %r5, 6, 7, 8
@@ -14259,22 +14259,22 @@
# CHECK: rsch
0xb2 0x38 0x00 0x00
-# CHECK: rxsbg %r0, %r0, 0, 0, 0
+# CHECK: rxsbg %r0, %r0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x57
# CHECK: rxsbg %r0, %r0, 0, 0, 63
0xec 0x00 0x00 0x00 0x3f 0x57
-# CHECK: rxsbg %r0, %r0, 0, 255, 0
+# CHECK: rxsbg %r0, %r0, 0, 255
0xec 0x00 0x00 0xff 0x00 0x57
-# CHECK: rxsbg %r0, %r0, 255, 0, 0
+# CHECK: rxsbg %r0, %r0, 255, 0
0xec 0x00 0xff 0x00 0x00 0x57
-# CHECK: rxsbg %r0, %r15, 0, 0, 0
+# CHECK: rxsbg %r0, %r15, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x57
-# CHECK: rxsbg %r15, %r0, 0, 0, 0
+# CHECK: rxsbg %r15, %r0, 0, 0
0xec 0xf0 0x00 0x00 0x00 0x57
# CHECK: rxsbg %r4, %r5, 6, 7, 8
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 93f5ff27780ab..4567c029c572e 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -13693,11 +13693,13 @@
rchp
+#CHECK: risbg %r0, %r0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x55]
#CHECK: risbgz %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
+#CHECK: risbgz %r0, %r0, 0, 255 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
#CHECK: risbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 127 # encoding: [0xec,0x00,0x00,0x00,0x7f,0x55]
@@ -13709,11 +13711,13 @@
#CHECK: risbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
#CHECK: risbgz %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x87,0x08,0x55]
+ risbg %r0,%r0,0,0
risbg %r0,%r0,0,0,0
risbg %r0,%r0,0,0,63
risbg %r0,%r0,0,0,64
risbg %r0,%r0,0,0,255
risbgz %r0,%r0,0,255,0
+ risbgz %r0,%r0,0,255
risbg %r0,%r0,0,255,0
risbg %r0,%r0,255,0,0
risbg %r0,%r0,0,0,127
@@ -13777,6 +13781,7 @@
rllg %r0,%r0,524287(%r1)
rllg %r0,%r0,524287(%r15)
+#CHECK: rnsbg %r0, %r0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x54]
#CHECK: rnsbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x54]
#CHECK: rnsbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x54]
#CHECK: rnsbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x54]
@@ -13787,6 +13792,7 @@
#CHECK: rnsbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x54]
#CHECK: rnsbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x54]
+ rnsbg %r0,%r0,0,0
rnsbg %r0,%r0,0,0,0
rnsbg %r0,%r0,0,0,63
rnsbg %r0,%r0,0,0,64
@@ -13797,6 +13803,7 @@
rnsbg %r15,%r0,0,0,0
rnsbg %r4,%r5,6,7,8
+#CHECK: rosbg %r0, %r0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x56]
#CHECK: rosbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x56]
#CHECK: rosbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x56]
#CHECK: rosbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x56]
@@ -13807,6 +13814,7 @@
#CHECK: rosbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x56]
#CHECK: rosbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x56]
+ rosbg %r0,%r0,0,0
rosbg %r0,%r0,0,0,0
rosbg %r0,%r0,0,0,63
rosbg %r0,%r0,0,0,64
@@ -13875,6 +13883,7 @@
rsch
+#CHECK: rxsbg %r0, %r0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x57]
#CHECK: rxsbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x57]
#CHECK: rxsbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x57]
#CHECK: rxsbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x57]
@@ -13885,6 +13894,7 @@
#CHECK: rxsbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x57]
#CHECK: rxsbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x57]
+ rxsbg %r0,%r0,0,0
rxsbg %r0,%r0,0,0,0
rxsbg %r0,%r0,0,0,63
rxsbg %r0,%r0,0,0,64
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