[llvm] d9fb3ce - AMDGPU: Remove accidentally committed tests
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 4 03:56:29 PST 2025
Author: Matt Arsenault
Date: 2025-03-04T18:56:00+07:00
New Revision: d9fb3cef5de1d1cd1261ae1753a578df1b9817de
URL: https://github.com/llvm/llvm-project/commit/d9fb3cef5de1d1cd1261ae1753a578df1b9817de
DIFF: https://github.com/llvm/llvm-project/commit/d9fb3cef5de1d1cd1261ae1753a578df1b9817de.diff
LOG: AMDGPU: Remove accidentally committed tests
Added:
Modified:
Removed:
llvm/test/CodeGen/AMDGPU/coalesces-better.mir
llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/coalesces-better.mir b/llvm/test/CodeGen/AMDGPU/coalesces-better.mir
deleted file mode 100644
index 593220d879c2a..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/coalesces-better.mir
+++ /dev/null
@@ -1,74 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 -start-after=si-fold-operands -o - %s | FileCheck %s
-
---- |
- target triple = "amdgcn-mesa-mesa3d"
-
- define <4 x float> @test_smfmac_f32_16x16x64_f16(<8 x half> %arg0, <16 x half> %arg1, <4 x float> %arg2, i32 %arg3) #0 {
- ; CHECK-LABEL: test_smfmac_f32_16x16x64_f16:
- ; CHECK: ; %bb.0:
- ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
- ; CHECK-NEXT: v_smfmac_f32_16x16x64_f16 v[12:15], v[0:3], v[4:11], v16
- ; CHECK-NEXT: s_nop 7
- ; CHECK-NEXT: v_mov_b32_e32 v0, v12
- ; CHECK-NEXT: v_mov_b32_e32 v1, v13
- ; CHECK-NEXT: v_mov_b32_e32 v2, v14
- ; CHECK-NEXT: v_mov_b32_e32 v3, v15
- ; CHECK-NEXT: s_setpc_b64 s[30:31]
- %result = call <4 x float> @llvm.amdgcn.smfmac.f32.16x16x64.f16(<8 x half> %arg0, <16 x half> %arg1, <4 x float> %arg2, i32 %arg3, i32 immarg 0, i32 immarg 0)
- ret <4 x float> %result
- }
-
- ; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
- declare <4 x float> @llvm.amdgcn.smfmac.f32.16x16x64.f16(<8 x half>, <16 x half>, <4 x float>, i32, i32 immarg, i32 immarg) #1
-
- attributes #0 = { "target-cpu"="gfx950" }
- attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx950" }
-
-...
----
-name: test_smfmac_f32_16x16x64_f16
-tracksRegLiveness: true
-isSSA: true
-machineFunctionInfo:
- frameOffsetReg: '$sgpr33'
- stackPtrOffsetReg: '$sgpr32'
- sgprForEXECCopy: '$sgpr100_sgpr101'
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16
-
-
- %0:vgpr_32 = COPY $vgpr16
- %1:vgpr_32 = COPY $vgpr15
- %2:vgpr_32 = COPY $vgpr14
- %3:vgpr_32 = COPY $vgpr13
- %4:vgpr_32 = COPY $vgpr12
- %5:vgpr_32 = COPY $vgpr11
- %6:vgpr_32 = COPY $vgpr10
- %7:vgpr_32 = COPY $vgpr9
- %8:vgpr_32 = COPY $vgpr8
- %9:vgpr_32 = COPY $vgpr7
- %10:vgpr_32 = COPY $vgpr6
- %11:vgpr_32 = COPY $vgpr5
- %12:vgpr_32 = COPY $vgpr4
- %13:vgpr_32 = COPY $vgpr3
- %14:vgpr_32 = COPY $vgpr2
- %15:vgpr_32 = COPY $vgpr1
- %16:vgpr_32 = COPY $vgpr0
- %17:vreg_256_align2 = REG_SEQUENCE %12, %subreg.sub0, %11, %subreg.sub1, %10, %subreg.sub2, %9, %subreg.sub3, %8, %subreg.sub4, %7, %subreg.sub5, %6, %subreg.sub6, %5, %subreg.sub7
- %18:vreg_128_align2 = REG_SEQUENCE %4, %subreg.sub0, %3, %subreg.sub1, %2, %subreg.sub2, %1, %subreg.sub3
- %19:vreg_128_align2 = REG_SEQUENCE %16, %subreg.sub0, %15, %subreg.sub1, %14, %subreg.sub2, %13, %subreg.sub3
- %24:areg_128_align2 = COPY %18
- %25:areg_128_align2 = V_SMFMAC_F32_16X16X64_F16_e64 %19, %17, %0, 0, 0, %24, implicit $mode, implicit $exec
- %26:vgpr_32 = COPY %25.sub0
- %27:vgpr_32 = COPY %25.sub1
- %28:vgpr_32 = COPY %25.sub2
- %29:vgpr_32 = COPY %25.sub3
- $vgpr0 = COPY %26
- $vgpr1 = COPY %27
- $vgpr2 = COPY %28
- $vgpr3 = COPY %29
- SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
-
-...
diff --git a/llvm/test/CodeGen/AMDGPU/coalesces-worse.mir b/llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
deleted file mode 100644
index 0718f825fbacb..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
+++ /dev/null
@@ -1,71 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 -start-after=si-fold-operands -o - %s | FileCheck %s
-
---- |
- target triple = "amdgcn-mesa-mesa3d"
-
- define <4 x float> @test_smfmac_f32_16x16x64_f16(<8 x half> %arg0, <16 x half> %arg1, <4 x float> %arg2, i32 %arg3) #0 {
- ; CHECK-LABEL: test_smfmac_f32_16x16x64_f16:
- ; CHECK: ; %bb.0:
- ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
- ; CHECK-NEXT: v_accvgpr_write_b32 a0, v12
- ; CHECK-NEXT: v_accvgpr_write_b32 a1, v13
- ; CHECK-NEXT: v_accvgpr_write_b32 a2, v14
- ; CHECK-NEXT: v_accvgpr_write_b32 a3, v15
- ; CHECK-NEXT: s_nop 1
- ; CHECK-NEXT: v_smfmac_f32_16x16x64_f16 a[0:3], v[0:3], v[4:11], v16
- ; CHECK-NEXT: s_nop 7
- ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
- ; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
- ; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
- ; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
- ; CHECK-NEXT: s_setpc_b64 s[30:31]
- %result = call <4 x float> @llvm.amdgcn.smfmac.f32.16x16x64.f16(<8 x half> %arg0, <16 x half> %arg1, <4 x float> %arg2, i32 %arg3, i32 immarg 0, i32 immarg 0)
- ret <4 x float> %result
- }
-
- declare <4 x float> @llvm.amdgcn.smfmac.f32.16x16x64.f16(<8 x half>, <16 x half>, <4 x float>, i32, i32 immarg, i32 immarg) #1
-
- attributes #0 = { "target-cpu"="gfx950" }
- attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx950" }
-
-...
----
-name: test_smfmac_f32_16x16x64_f16
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16
-
- %0:vgpr_32 = COPY $vgpr16
- %1:vgpr_32 = COPY $vgpr15
- %2:vgpr_32 = COPY $vgpr14
- %3:vgpr_32 = COPY $vgpr13
- %4:vgpr_32 = COPY $vgpr12
- %5:vgpr_32 = COPY $vgpr11
- %6:vgpr_32 = COPY $vgpr10
- %7:vgpr_32 = COPY $vgpr9
- %8:vgpr_32 = COPY $vgpr8
- %9:vgpr_32 = COPY $vgpr7
- %10:vgpr_32 = COPY $vgpr6
- %11:vgpr_32 = COPY $vgpr5
- %12:vgpr_32 = COPY $vgpr4
- %13:vgpr_32 = COPY $vgpr3
- %14:vgpr_32 = COPY $vgpr2
- %15:vgpr_32 = COPY $vgpr1
- %16:vgpr_32 = COPY $vgpr0
- %17:vreg_256_align2 = REG_SEQUENCE %12, %subreg.sub0, %11, %subreg.sub1, %10, %subreg.sub2, %9, %subreg.sub3, %8, %subreg.sub4, %7, %subreg.sub5, %6, %subreg.sub6, %5, %subreg.sub7
- %18:vreg_128_align2 = REG_SEQUENCE %4, %subreg.sub0, %3, %subreg.sub1, %2, %subreg.sub2, %1, %subreg.sub3
- %19:vreg_128_align2 = REG_SEQUENCE %16, %subreg.sub0, %15, %subreg.sub1, %14, %subreg.sub2, %13, %subreg.sub3
- %20:areg_128_align2 = V_SMFMAC_F32_16X16X64_F16_e64 %19, %17, %0, 0, 0, %18, implicit $mode, implicit $exec
- %21:vgpr_32 = COPY %20.sub0
- %22:vgpr_32 = COPY %20.sub1
- %23:vgpr_32 = COPY %20.sub2
- %24:vgpr_32 = COPY %20.sub3
- $vgpr0 = COPY %21
- $vgpr1 = COPY %22
- $vgpr2 = COPY %23
- $vgpr3 = COPY %24
- SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
-
-...
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